RTAX250SL-CG624E vs RTAX250SL-1CG624E तुलना
विस्तृत दोनों ओर की तुलना RTAX250SL-CG624E द्वारा Microchip Technology और RTAX250SL-1CG624E द्वारा Microchip Technology. मुख्य विशेषताओं, इलेक्ट्रिकल पैरामीटर, पैकेजिंग, चक्र स्थिति, मूल्यांकन और उपलब्धता को तुलना करके अपनी डिजाइन की आवश्यकताओं के लिए सबसे अच्छा घटक निर्धारित करें。
Microchip Technology
RTAX250SL-CG624E - 250K-Gate Rad-Tolerant FPGA | Microchip
RTAX250SL-CG624E ✓ सक्रियMicrochip Technology
RTAX250SL-1CG624E - 250K Gate Rad-Tolerant FPGA, CCGA-624 | Microchip
RTAX250SL-1CG624E ✓ सक्रियविशेषता तुलना
| पैरामीटर | RTAX250SL-CG624E | RTAX250SL-1CG624E |
|---|---|---|
| ब्रांड | Microchip Technology | Microchip Technology |
| श्रेणी | FPGA & CPLD | FPGA & CPLD |
| लाइफसाइकिल स्थिति | सक्रिय | सक्रिय |
| Family | RTAX-S/SL Radiation-Tolerant FPGA | — |
| System Gates | 250000 | — |
| Logic Cells (CLBs) | 2816 | — |
| Maximum Frequency | 649 MHz | — |
| Process Technology | 0.15 um CMOS | 0.15 um CMOS |
| Core Supply Voltage | 1.5 V | 1.5 V (1.425 V to 1.575 V) |
| Supply Voltage Tolerance | +/-0.15 V | — |
| Maximum Combinatorial Delay | 0.93 ns | — |
| पैकेज | 624-Pin CCGA (Ceramic Column Grid Array) | 624-ball Ceramic Column Grid Array (CCGA-624) |
| ऑपरेटिंग तापमान | -55C to +125C | -55C to +125C |
| Logic Family | CMOS | CMOS |
| Radiation Tolerance | SEU-hardened registers; SEU rate < 10-10 errors/bit-day | SEU-immune to specified LET threshold; SEU rate < 10-10 errors/bit-day |
| Embedded Memory | Embedded SRAM with built-in FIFO control logic | Embedded SRAM with built-in FIFO control logic |
| Clocking | Segmentable clocks, chip-wide highway routing | — |
| माउंटिंग प्रकार | Surface Mount | Surface Mount (ceramic column grid array) |
| RoHS स्थिति | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Programmability | Live at power-up, true single-chip | — |
| Equivalent System Gates | — | 250,000 gates |
| Configurable Logic Blocks (CLBs) | — | 2816 |
| Logic Cells | — | 4224 |
| User I/O | — | 248 inputs / 248 outputs |
| Maximum Combinatorial Delay (CLB) | — | 0.93 ns |
| Maximum System Frequency | — | 649 MHz |
| SEU Mitigation | — | SEU-hardened registers (no external TMR required) |
| Configuration | — | Live-at-power-up, true single-chip operation |
| I/O Supply Voltage | — | [DATA_NEEDED: I/O bank voltage] |