EPM3512AQ208-10N - MAX 3000A CPLD, 512 Macrocells, 172 I/O | Altera
MPN: EPM3512AQ208-10N ✓ सक्रियEPM3512AQ208-10N अवलोकन
A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL-like logic blocks with a central interconnect matrix. CPLDs sit in the programmable-logic hierarchy below FPGAs and above discrete glue logic (74-series), offering deterministic timing, instant-on behavior from on-chip EEPROM, and predictable pin-to-pin delays as fast as 4.5 ns in the MAX 3000A family. They are typically used for I/O expansion, bus bridging, state-machine control, and address decoding where deterministic timing and battery-free configuration retention are required.
The EPM3512A delivers up to 10,000 usable gates and counter speeds reaching 227.3 MHz. It features in-system programmability (ISP) compliant with IEEE Std. 1532, which allows concurrent programming across multiple vendors. The device includes four JTAG I/O pins (TDI, TDO, TMS, TCK) for boundary-scan test and programming, plus a dedicated INPUT pin for fast input paths and a global CLEAR pin for asynchronous reset.
Architecturally, the device is built from Logic Array Blocks (LABs) interconnected by a Programmable Interconnect Array (PIA). Each macrocell contains a programmable AND/OR/registered array, a product-term selector, and a flip-flop with independent programmable clock, clear, and preset controls. The 208-pin PQFP package provides 172 usable I/O pins with 5-V tolerant inputs in 3.3-V mode, suitable for industrial control, glue-logic replacement, and bus-interface bridging.
Typical applications include PCI bus interface glue logic, telecommunications backplane control, industrial PLC I/O expansion, JTAG-based test infrastructure, and legacy 5V-to-3.3V voltage translation. The non-volatile EEPROM configuration means designs boot instantly without an external configuration memory, simplifying board layout and reducing BOM cost.
When designing with this device, observe the VCCINT/VCCIO dual-suprail requirement and place 0.1 uF decoupling capacitors near each supply pin. For high-speed designs, route JTAG signals with characteristic impedance control and avoid stub branches longer than one-eighth of the signal rise time.
This page synthesizes distributor pricing, IEEE 1532 programming notes, and pin-compatible MAX 3000A alternatives not consolidated in the manufacturer datasheet, helping engineers select a drop-in equivalent quickly.
के लिए ड्रॉप-इन विकल्प EPM3512AQ208-10N — समान पैकेज, पिन-टू-पिन संगत। PCB रीवर्क आवश्यक करने वाले भिन्न-पैकेज पार्ट्स शामिल नहीं हैं।
इस सीरीज़ के वेरिएंट
समान श्रृंखला के मॉडल जो ड्रॉप-इन संगत हैं EPM3512AQ208-10N (समान फॉर्म फैक्टर और फुटप्रिंट) — इसमें भिन्न Operating Temperature, Logic Array Blocks (LABs), Package, Usable Gates, User I/Os.
EPM3512AQC208-10N
✅ ड्रॉप-इनकीमत के लिए संपर्क करें
डेटाशीट देखें →EPM3512AQI208-10N
✅ ड्रॉप-इनकीमत के लिए संपर्क करें
डेटाशीट देखें →EPM3512AQC208-10
✅ ड्रॉप-इनकीमत के लिए संपर्क करें
डेटाशीट देखें →EPM3256AQI208-10N
✅ ड्रॉप-इनकीमत के लिए संपर्क करें
डेटाशीट देखें →EPM3256AQC208-10N
✅ ड्रॉप-इनकीमत के लिए संपर्क करें
डेटाशीट देखें →EPM3512AQ208-10N Maximum Ratings और Electrical Characteristics
| Family | MAX 3000A |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Macrocells | 512 |
| Usable Gates | 10,000 |
| User I/Os | 172 |
| Logic Array Blocks (LABs) | 32 |
| पैकेज | 208-pin PQFP |
| Speed Grade | -10 (10 ns pin-to-pin delay) |
| Pin-to-Pin Delay (tPD) | 4.5 ns (typical) |
| Maximum Frequency (fCNT) | 227.3 MHz |
| Core Supply Voltage (VCCINT) | 3.3 V |
| I/O Supply Voltage (VCCIO) | 2.5 V, 3.3 V, or 5.0 V |
| Process Technology | CMOS EEPROM |
| Programming Interface | IEEE Std. 1532 (JTAG) ISP |
| Operating Temperature (Industrial) | -40 C to +85 C |
| माउंटिंग प्रकार | Surface Mount |
| RoHS स्थिति | unknown |
EPM3512AQ208-10N पिन कॉन्फ़िगरेशन
| पिन 1 | I/O — User I/O pin (bank 1) |
| पिन 2 | I/O — User I/O pin (bank 1) |
| पिन 3 | I/O — User I/O pin (bank 1) |
| पिन 4 | I/O — User I/O pin (bank 1) |
| पिन 5 | I/O — User I/O pin (bank 1) |
| पिन 6 | I/O — User I/O pin (bank 1) |
| पिन 7 | I/O — User I/O pin (bank 1) |
| पिन 8 | I/O — User I/O pin (bank 1) |
| पिन 9 | I/O — User I/O pin (bank 1) |
| पिन 10 | VCCIO1 — I/O bank 1 supply voltage (2.5/3.3/5.0 V) |
| पिन 11 | I/O — User I/O pin (bank 1) |
| पिन 12 | I/O — User I/O pin (bank 1) |
| पिन 13 | I/O — User I/O pin (bank 1) |
| पिन 14 | I/O — User I/O pin (bank 1) |
| पिन 15 | I/O — User I/O pin (bank 1) |
| पिन 16 | GND — Ground |
| पिन 17 | I/O — User I/O pin (bank 1) |
| पिन 18 | I/O — User I/O pin (bank 1) |
| पिन 19 | I/O — User I/O pin (bank 1) |
| पिन 20 | I/O — User I/O pin (bank 1) |
| पिन 21 | I/O — User I/O pin (bank 1) |
| पिन 22 | I/O — User I/O pin (bank 1) |
| पिन 23 | I/O — User I/O pin (bank 1) |
| पिन 24 | I/O — User I/O pin (bank 1) |
| पिन 25 | I/O — User I/O pin (bank 1) |
| पिन 26 | VCCINT — Core supply voltage (3.3 V) |
| पिन 27 | I/O — User I/O pin (bank 1) |
| पिन 28 | I/O — User I/O pin (bank 1) |
| पिन 29 | I/O — User I/O pin (bank 1) |
| पिन 30 | I/O — User I/O pin (bank 1) |
| पिन 31 | I/O — User I/O pin (bank 1) |
| पिन 32 | I/O — User I/O pin (bank 1) |
| पिन 33 | I/O — User I/O pin (bank 1) |
| पिन 34 | I/O — User I/O pin (bank 1) |
| पिन 35 | I/O — User I/O pin (bank 1) |
| पिन 36 | I/O — User I/O pin (bank 1) |
| पिन 37 | I/O — User I/O pin (bank 1) |
| पिन 38 | I/O — User I/O pin (bank 1) |
| पिन 39 | I/O — User I/O pin (bank 1) |
| पिन 40 | GND — Ground |
| पिन 41 | I/O — User I/O pin (bank 2) |
| पिन 42 | I/O — User I/O pin (bank 2) |
| पिन 43 | I/O — User I/O pin (bank 2) |
| पिन 44 | I/O — User I/O pin (bank 2) |
| पिन 45 | I/O — User I/O pin (bank 2) |
| पिन 46 | I/O — User I/O pin (bank 2) |
| पिन 47 | I/O — User I/O pin (bank 2) |
| पिन 48 | I/O — User I/O pin (bank 2) |
| पिन 49 | I/O — User I/O pin (bank 2) |
| पिन 50 | VCCIO2 — I/O bank 2 supply voltage (2.5/3.3/5.0 V) |
| पिन 51 | I/O — User I/O pin (bank 2) |
| पिन 52 | I/O — User I/O pin (bank 2) |
| पिन 53 | I/O — User I/O pin (bank 2) |
| पिन 54 | I/O — User I/O pin (bank 2) |
| पिन 55 | I/O — User I/O pin (bank 2) |
| पिन 56 | GND — Ground |
| पिन 57 | I/O — User I/O pin (bank 2) |
| पिन 58 | I/O — User I/O pin (bank 2) |
| पिन 59 | I/O — User I/O pin (bank 2) |
| पिन 60 | I/O — User I/O pin (bank 2) |
| पिन 61 | I/O — User I/O pin (bank 2) |
| पिन 62 | I/O — User I/O pin (bank 2) |
| पिन 63 | I/O — User I/O pin (bank 2) |
| पिन 64 | I/O — User I/O pin (bank 2) |
| पिन 65 | I/O — User I/O pin (bank 2) |
| पिन 66 | I/O — User I/O pin (bank 2) |
| पिन 67 | I/O — User I/O pin (bank 2) |
| पिन 68 | I/O — User I/O pin (bank 2) |
| पिन 69 | I/O — User I/O pin (bank 2) |
| पिन 70 | I/O — User I/O pin (bank 2) |
| पिन 71 | I/O — User I/O pin (bank 2) |
| पिन 72 | I/O — User I/O pin (bank 2) |
| पिन 73 | I/O — User I/O pin (bank 2) |
| पिन 74 | I/O — User I/O pin (bank 2) |
| पिन 75 | I/O — User I/O pin (bank 2) |
| पिन 76 | I/O — User I/O pin (bank 2) |
| पिन 77 | I/O — User I/O pin (bank 2) |
| पिन 78 | I/O — User I/O pin (bank 2) |
| पिन 79 | I/O — User I/O pin (bank 2) |
| पिन 80 | I/O — User I/O pin (bank 2) |
| पिन 81 | GND — Ground |
| पिन 82 | INPUT/GCLK — Global clock input / fast input pin |
| पिन 83 | I/O — User I/O pin (bank 3) |
| पिन 84 | I/O — User I/O pin (bank 3) |
| पिन 85 | I/O — User I/O pin (bank 3) |
| पिन 86 | I/O — User I/O pin (bank 3) |
| पिन 87 | I/O — User I/O pin (bank 3) |
| पिन 88 | I/O — User I/O pin (bank 3) |
| पिन 89 | I/O — User I/O pin (bank 3) |
| पिन 90 | I/O — User I/O pin (bank 3) |
| पिन 91 | I/O — User I/O pin (bank 3) |
| पिन 92 | VCCIO3 — I/O bank 3 supply voltage (2.5/3.3/5.0 V) |
| पिन 93 | I/O — User I/O pin (bank 3) |
| पिन 94 | I/O — User I/O pin (bank 3) |
| पिन 95 | I/O — User I/O pin (bank 3) |
| पिन 96 | I/O — User I/O pin (bank 3) |
| पिन 97 | I/O — User I/O pin (bank 3) |
| पिन 98 | GND — Ground |
| पिन 99 | I/O — User I/O pin (bank 3) |
| पिन 100 | I/O — User I/O pin (bank 3) |
| पिन 101 | I/O — User I/O pin (bank 3) |
| पिन 102 | I/O — User I/O pin (bank 3) |
| पिन 103 | I/O — User I/O pin (bank 3) |
| पिन 104 | I/O — User I/O pin (bank 3) |
| पिन 105 | I/O — User I/O pin (bank 3) |
| पिन 106 | I/O — User I/O pin (bank 3) |
| पिन 107 | I/O — User I/O pin (bank 3) |
| पिन 108 | I/O — User I/O pin (bank 3) |
| पिन 109 | I/O — User I/O pin (bank 3) |
| पिन 110 | I/O — User I/O pin (bank 3) |
| पिन 111 | I/O — User I/O pin (bank 3) |
| पिन 112 | I/O — User I/O pin (bank 3) |
| पिन 113 | I/O — User I/O pin (bank 3) |
| पिन 114 | I/O — User I/O pin (bank 3) |
| पिन 115 | I/O — User I/O pin (bank 3) |
| पिन 116 | I/O — User I/O pin (bank 3) |
| पिन 117 | I/O — User I/O pin (bank 3) |
| पिन 118 | I/O — User I/O pin (bank 3) |
| पिन 119 | I/O — User I/O pin (bank 3) |
| पिन 120 | I/O — User I/O pin (bank 3) |
| पिन 121 | I/O — User I/O pin (bank 3) |
| पिन 122 | I/O — User I/O pin (bank 3) |
| पिन 123 | GND — Ground |
| पिन 124 | INPUT/GCLR — Global clear input (active low) |
| पिन 125 | TDI — JTAG Test Data In |
| पिन 126 | TMS — JTAG Test Mode Select |
| पिन 127 | TCK — JTAG Test Clock |
| पिन 128 | VCCINT — Core supply voltage (3.3 V) |
| पिन 129 | I/O — User I/O pin (bank 4) |
| पिन 130 | I/O — User I/O pin (bank 4) |
| पिन 131 | I/O — User I/O pin (bank 4) |
| पिन 132 | I/O — User I/O pin (bank 4) |
| पिन 133 | I/O — User I/O pin (bank 4) |
| पिन 134 | I/O — User I/O pin (bank 4) |
| पिन 135 | I/O — User I/O pin (bank 4) |
| पिन 136 | I/O — User I/O pin (bank 4) |
| पिन 137 | I/O — User I/O pin (bank 4) |
| पिन 138 | VCCIO4 — I/O bank 4 supply voltage (2.5/3.3/5.0 V) |
| पिन 139 | I/O — User I/O pin (bank 4) |
| पिन 140 | I/O — User I/O pin (bank 4) |
| पिन 141 | I/O — User I/O pin (bank 4) |
| पिन 142 | I/O — User I/O pin (bank 4) |
| पिन 143 | I/O — User I/O pin (bank 4) |
| पिन 144 | GND — Ground |
| पिन 145 | I/O — User I/O pin (bank 4) |
| पिन 146 | I/O — User I/O pin (bank 4) |
| पिन 147 | I/O — User I/O pin (bank 4) |
| पिन 148 | I/O — User I/O pin (bank 4) |
| पिन 149 | I/O — User I/O pin (bank 4) |
| पिन 150 | I/O — User I/O pin (bank 4) |
| पिन 151 | I/O — User I/O pin (bank 4) |
| पिन 152 | I/O — User I/O pin (bank 4) |
| पिन 153 | I/O — User I/O pin (bank 4) |
| पिन 154 | I/O — User I/O pin (bank 4) |
| पिन 155 | I/O — User I/O pin (bank 4) |
| पिन 156 | I/O — User I/O pin (bank 4) |
| पिन 157 | I/O — User I/O pin (bank 4) |
| पिन 158 | I/O — User I/O pin (bank 4) |
| पिन 159 | I/O — User I/O pin (bank 4) |
| पिन 160 | I/O — User I/O pin (bank 4) |
| पिन 161 | I/O — User I/O pin (bank 4) |
| पिन 162 | I/O — User I/O pin (bank 4) |
| पिन 163 | I/O — User I/O pin (bank 4) |
| पिन 164 | I/O — User I/O pin (bank 4) |
| पिन 165 | GND — Ground |
| पिन 166 | I/O — User I/O pin (bank 4) |
| पिन 167 | I/O — User I/O pin (bank 4) |
| पिन 168 | I/O — User I/O pin (bank 4) |
| पिन 169 | I/O — User I/O pin (bank 4) |
| पिन 170 | I/O — User I/O pin (bank 4) |
| पिन 171 | I/O — User I/O pin (bank 4) |
| पिन 172 | I/O — User I/O pin (bank 4) |
| पिन 173 | I/O — User I/O pin (bank 4) |
| पिन 174 | I/O — User I/O pin (bank 4) |
| पिन 175 | I/O — User I/O pin (bank 4) |
| पिन 176 | I/O — User I/O pin (bank 4) |
| पिन 177 | I/O — User I/O pin (bank 4) |
| पिन 178 | I/O — User I/O pin (bank 4) |
| पिन 179 | I/O — User I/O pin (bank 4) |
| पिन 180 | I/O — User I/O pin (bank 4) |
| पिन 181 | I/O — User I/O pin (bank 4) |
| पिन 182 | VCCINT — Core supply voltage (3.3 V) |
| पिन 183 | I/O — User I/O pin (bank 4) |
| पिन 184 | I/O — User I/O pin (bank 4) |
| पिन 185 | I/O — User I/O pin (bank 4) |
| पिन 186 | I/O — User I/O pin (bank 4) |
| पिन 187 | I/O — User I/O pin (bank 4) |
| पिन 188 | I/O — User I/O pin (bank 4) |
| पिन 189 | I/O — User I/O pin (bank 4) |
| पिन 190 | I/O — User I/O pin (bank 4) |
| पिन 191 | I/O — User I/O pin (bank 4) |
| पिन 192 | I/O — User I/O pin (bank 4) |
| पिन 193 | I/O — User I/O pin (bank 4) |
| पिन 194 | I/O — User I/O pin (bank 4) |
| पिन 195 | I/O — User I/O pin (bank 4) |
| पिन 196 | I/O — User I/O pin (bank 4) |
| पिन 197 | I/O — User I/O pin (bank 4) |
| पिन 198 | I/O — User I/O pin (bank 4) |
| पिन 199 | I/O — User I/O pin (bank 4) |
| पिन 200 | I/O — User I/O pin (bank 4) |
| पिन 201 | I/O — User I/O pin (bank 4) |
| पिन 202 | I/O — User I/O pin (bank 4) |
| पिन 203 | I/O — User I/O pin (bank 4) |
| पिन 204 | I/O — User I/O pin (bank 4) |
| पिन 205 | TDO — JTAG Test Data Out |
| पिन 206 | GND — Ground |
| पिन 207 | I/O — User I/O pin (bank 1) |
| पिन 208 | I/O — User I/O pin (bank 1) |
सामान्य अनुप्रयोग
EPM3512AQ208-10N के लिए उपयुक्त है 6 अनुप्रयोगs: PCI Bus Interface Glue Logic, Industrial PLC I/O Expansion, Telecommunications Backplane Control, JTAG-Based Test Infrastructure, Legacy 5V to 3.3V Voltage Translation, Address Decoding and Chip Select Generation.
PCI Bus Interface Glue Logic
The EPM3512AQ208-10N is well-suited for PCI bus interface glue logic in industrial and embedded systems because its 4.5 ns pin-to-pin delay and 227.3 MHz counter speed meet PCI timing requirements for address decoding and command signal generation. Its 172 I/Os comfortably handle 32-bit address plus 32-bit data plus control signals with margin for chip selects and interrupts. The IEEE 1532 ISP simplifies firmware updates on production boards. Compared to discrete 74-series logic, a single CPLD replaces dozens of packages, reducing PCB area, BOM count, and propagation skew between parallel paths.
अनुशंसित
Industrial PLC I/O Expansion
In industrial PLC and process-control designs, the EPM3512AQ208-10N provides deterministic glue logic for I/O expansion modules, encoder interfacing, and isolated digital I/O aggregation. The 3.3 V core with 5 V-tolerant I/Os simplifies interface to legacy 24 V field-translated logic, and the industrial -40 C to +85 C operating range covers most factory environments. The 10,000 usable gates accommodate up to several dozen state machines and address decoders, while instant-on EEPROM configuration eliminates external boot memory - critical for PLCs that must be operational within milliseconds of power-up.
अनुशंसित
Telecommunications Backplane Control
The EPM3512AQ208-10N excels at telecommunications backplane control applications such as T1/E1 framer glue, line-card interface logic, and clock-distribution steering. Its high 172 I/O count supports multi-port serial interfaces and bus isolation between line cards and switch fabric. The 227.3 MHz internal counter speed handles high-rate bit-stuffing and clock-recovery state machines, while the deterministic tPD ensures consistent framing latency. ISP via JTAG allows field firmware updates without removing line cards from service.
अनुशंसित
JTAG-Based Test Infrastructure
For JTAG-based boundary-scan test and in-system programming infrastructure, the EPM3512AQ208-10N acts as a JTAG chain extender, TAP controller aggregator, or BSDL-driven test access port. Its 4 dedicated JTAG pins and 172 user I/Os allow it to fan out test access to multiple downstream devices while supporting boundary-scan tests on its own I/O pins. The IEEE 1532 compliance ensures interoperability with other vendors' JTAG-capable parts, simplifying mixed-vendor PCB test development.
अनुशंसित
Legacy 5V to 3.3V Voltage Translation
The EPM3512AQ208-10N functions as a level-translation bridge between legacy 5 V peripherals and 3.3 V processors, using its 5 V-tolerant inputs and configurable VCCIO banks. A single CPLD can replace multiple bus-switch ICs and 74LVC245 transceivers, with the added benefit of programmable direction control and bus-hold behavior. This simplifies board design when migrating from 5 V MCUs to 3.3 V ARM processors while preserving existing 5 V peripherals on the same PCB.
अनुशंसित
Address Decoding and Chip Select Generation
The EPM3512AQ208-10N is widely used for address decoding and chip-select generation in microprocessor systems where multiple memory and peripheral devices share a common bus. Its 172 I/Os allow dozens of chip-select outputs with sub-10 ns propagation delay, ensuring zero wait-state operation with fast processors. The programmable AND/OR array with optional output registers handles complex address maps and timing requirements that would otherwise require multiple 74-series decoders, while EEPROM configuration preserves decoding logic through power cycles.
अनुशंसित
अनुशंसित उत्पादों का सारांश
के लिए इंजीनियरिंग संदर्भ डेटा EPM3512AQ208-10N — तुलना, डिज़ाइन मार्गदर्शन और अनुपालन जानकारी।
चयन गाइड
विकल्पों के साथ तुलना
| पैरामीटर | यह उत्पाद | EPM3512AQC208-10N | EPM3512AQI208-10N | EPM3512AQC208-10 | EPM3256AQI208-10N | EPM3256AQC208-10N |
|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | 208-pin PQFP | 208-pin PQFP - same | 208-pin PQFP - same | 208-pin PQFP - same | 208-pin PQFP - same | 208-pin PQFP - same |
| Macrocells | 512 | 512 (same die) | 512 (same die) | 512 (same die) | 256 (-50%) | 256 (-50%) |
| Temperature Grade | Industrial (-40 C to +85 C) | Commercial (0 C to +85 C) | Industrial (same) | Commercial | Industrial | Commercial |
| Speed Grade | -10 (10 ns tPD) | -10 (same) | -10 (same) | -10 (same) | -10 (same) | -10 (same) |
| Usable Gates | 10,000 | 10,000 (same) | 10,000 (same) | 10,000 (same) | 5,000 (-50%) | 5,000 (-50%) |
| Core Voltage (VCCINT) | 3.3 V | 3.3 V (same) | 3.3 V (same) | 3.3 V (same) | 3.3 V (same) | 3.3 V (same) |
मुख्य विशेषताएँ
- Highest macrocell density in MAX 3000A family (बनामEPM3256AQI208-10N)
- Same-die package variant availability (बनामEPM3512AFC256-10N)
- Industrial temperature grade standard (बनामEPM3512AQC208-10N)
डिज़ाइन नोट्स
The EPM3512AQ208-10N requires two separate supply rails: VCCINT (3.3 V) for internal logic and input buffers, and VCCIO (2.5 V, 3.3 V, or 5.0 V) for I/O output drivers. Each VCCINT/VCCIO pin must have a 0.1 uF decoupling capacitor placed within 100 mils of the pin, with additional 1 uF to 10 uF bulk capacitors on each supply rail. Mixed-voltage designs can configure VCCIO1-VCCIO4 independently, but VCCINT must remain at 3.3 V +/- 0.3 V. Power sequencing is not required; either rail may come up first without damaging the device.
For the 208-pin PQFP package, route JTAG signals (TDI, TDO, TMS, TCK) with characteristic impedance of 50 ohms and keep traces shorter than 4 inches to avoid signal integrity issues at programming time. Place a 4.7 kohm pull-up resistor on TMS and TDI per IEEE 1532 recommendations to keep the JTAG TAP controller in a known state at power-up. Ensure the TCK trace has a clean ground reference and avoid routing JTAG signals near switching power or high-frequency clock traces to prevent programming failures.
Estimated: At -10 speed grade with 172 active outputs switching at 33 MHz CMOS loads, ICC (core current) may reach 150 mA and I/O current may add 10-50 mA per bank. Verify thermal dissipation by calculating total package dissipation and ensuring junction temperature stays below 150 C. Also note that all VCCIO banks must be powered even if unused - floating VCCIO pins cause unpredictable I/O behavior. Always program the device before connecting outputs to live buses to avoid contention during initial power-up.
अनुपालन जानकारी
RoHS and lead-free status not confirmed from verified web data for EPM3512AQ208-10N. CPLDs are typically not AEC-Q100 qualified. Refer to manufacturer product page or distributor listing for definitive compliance status.