10AX115H2F34E2SG vs 10AX115U3F45E2SG Perbandingan
Perbandingan bersamaan detil 10AX115H2F34E2SG dari Intel dan 10AX115U3F45E2SG dari Intel. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.
Perbandingan Spesifikasi
| Parameter Umum | 10AX115H2F34E2SG | 10AX115U3F45E2SG |
|---|---|---|
| Merek | Intel | Intel |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Aktif | Aktif |
| Series | Arria 10 GX | — |
| Logic Elements (LE) | 1,150,000 | 1,150,000 |
| Adaptive Logic Modules (ALM) | 427,200 | 427,200 |
| Embedded Memory (M20K blocks) | 2,713 blocks / 68,857,600 bits | — |
| User I/O Pins | 504 | — |
| Transceivers | 24 channels up to 14.1 Gbps | — |
| PCIe Hard IP | Gen3 x4 / Gen2 x8 | — |
| Hard Processor System | Dual-core ARM Cortex-A9 MPCore | — |
| DSP Blocks | Hardened IEEE 754 single/double-precision floating-point | Variable-precision, hardened floating-point |
| 18x19 Multipliers | 2,150 | — |
| PLLs | Fractional, up to 24 | — |
| Memory Interfaces | DDR4 up to 1,600 Mbps, DDR3, QDRII+, RLDRAM3 | — |
| Paket | 1152-ball FCBGA (F34) 35x35 mm | 1932-ball FCBGA (F45, 45×45 mm, 1.0 mm pitch) |
| Speed/Operating Temperature Grade | -2 / 0 C to 100 C (E2 = industrial, enhanced) | — |
| Process Node | 20 nm Tri-Gate (Intel) | 20 nm Tri-Gate (Intel) |
| Tipe Mounting | Surface Mount (BGA) | — |
| Status RoHS | Compliant | — |
| Family | — | Arria 10 GX |
| Embedded Memory Bits | — | 68,857,856 (≈ 52.99 Mbit) |
| Number of Transceivers | — | [DATA_NEEDED: per-die transceiver count, F45 package variant] |
| Maximum Transceiver Data Rate | — | 17.4 Gbps |
| Hard Memory Controllers | — | 2 (DDR4/DDR3/QDRII+/RLDRAM3) |
| Hard PCIe Gen3 IP Blocks | — | 2 × PCIe Gen3 (x8/x4/x2/x1) |
| Speed Grade | — | -2 (E2 commercial/extended) |
| Suhu Kerja | — | Industrial (junction -40 °C to +100 °C) – device grade U |
| Supply Voltage Core | — | [DATA_NEEDED: VCC/VCCP core voltage] |
| Configuration Method | — | FPGA configuration via serial/parallel flash, JTAG |
| RoHS Compliance | — | Compliant |
| Level MSL | — | [DATA_NEEDED: MSL rating per JEDEC J-STD-020] |