5M240ZT144I5N vs 5M1270ZT144C5N Perbandingan

Perbandingan bersamaan detil 5M240ZT144I5N dari Intel dan 5M1270ZT144C5N dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.

Perbandingan Spesifikasi

Parameter Umum 5M240ZT144I5N 5M1270ZT144C5N
Merek Intel Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Aktif Aktif
Family MAX V —
Device Logic Elements 240 LE —
Number of Logic Array Blocks 12 LAB —
Maximum User I/O Pins 114 —
User Flash Memory (UFM) 8 Kbits 8 Kbits
Internal Core Voltage 1.8 V —
I/O Bank Voltage 1.2 V to 3.3 V (multi-voltage) —
Speed Grade I5 (industrial, -40 C to +100 C) —
Paket TQFP-144 (T144) 22x22 mm TQFP-144 (22 x 22 mm, 0.5 mm pitch)
Tipe Mounting Surface Mount Surface Mount
Suhu Kerja -40 C to +100 C (industrial) 0 C to +85 C (commercial grade)
Configuration Memory Non-volatile (flash) Flash (non-volatile, in-system programmable)
Programming Interface JTAG (IEEE 1149.1) JTAG in-system programmable (Altera Quartus II)
Standby Current (typical) <1 mA —
Status RoHS Compliant Compliant
Device Type — CPLD (Complex Programmable Logic Device)
Series — MAX V
Logic Elements — 1270
Macrocells — 980
User I/Os — 114
Maximum Internal Frequency — 118.3 MHz
Pin-to-Pin Propagation Delay (tPD) — 6.2 ns
Internal Frequency (typical) — 201 MHz
VCCINT (Core Supply) — 1.71 V to 1.89 V
VCCIO (I/O Supply, per bank) — 1.2 V to 3.3 V
Number of I/O Banks — 4
Supported I/O Standards — LVCMOS, LVTTL, PCI up to 3.3 V, 1.2 V to 3.3 V LVCMOS on JTAG pins
JTAG Interface — IEEE 1149.1 (TMS, TDI, TDO, TCK in Bank 1)
Program/Erase Cycles — Up to 100,000

Spek dan Sumber

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