EP1AGX50DF1152C5N vs EP1AGX50DF1152I4N Perbandingan
Perbandingan bersamaan detil EP1AGX50DF1152C5N dari Intel dan EP1AGX50DF1152I4N dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.
Intel
EP1AGX50DF1152C5N - 50K LE Arria GX FPGA with 3.125 Gbps Transceivers | Intel
EP1AGX50DF1152C5N ⚠ Waktu Beli TerakhirPerbandingan Spesifikasi
| Parameter Umum | EP1AGX50DF1152C5N | EP1AGX50DF1152I4N |
|---|---|---|
| Merek | Intel | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Waktu Pembelian Terakhir | NRND |
| Family | Arria GX | Arria GX |
| Logic Elements (LE) | 50,160 | 50160 |
| Embedded Memory Bits | 2,475,072 bits | — |
| Embedded Multipliers (18x18) | 244 | — |
| Transceiver Channels | 8 full-duplex (up to 3.125 Gbps) | — |
| Maximum Transceiver Data Rate | 3.125 Gbps per channel | — |
| PLLs | 4 | — |
| Maximum User I/O Pins | 281 | — |
| Paket | 1152-ball FineLine BGA (FBGA-1152) | 1152-ball FineLine BGA |
| Speed Grade | -5 (commercial, slowest grade) | I4 |
| Process Technology | 90 nm CMOS, 1.2 V core | — |
| Operating Temperature (Commercial) | 0 C to +85 C (TJ) | — |
| Supply Voltage (Core) | 1.2 V | — |
| Supply Voltage (Auxiliary/PLL) | 2.5 V / 3.3 V | — |
| Status RoHS | Compliant (Pb-free) | — |
| Configuration Scheme | Active Serial (AS), Passive Serial (PS), JTAG, Fast Passive Parallel (FPP) | — |
| Supported Serial Protocols | PCIe Gen1 x1/x4, Gigabit Ethernet, Serial RapidIO, CEI-6G SR | — |
| User I/O Pins | — | 514 |
| Embedded Memory | — | 2475072 bits |
| Maximum User I/O Banks | — | [DATA_NEEDED: number of IO banks] |
| Transceivers | — | Up to 3.125 Gbps multi-gigabit transceivers |
| Suhu Kerja | — | -40C to +100C (Industrial) |
| Tipe Mounting | — | Surface Mount |
| Level MSL | — | [DATA_NEEDED: MSL level] |
| Lead-Free / RoHS | — | Yes (RoHS Compliant) |
| Process Node | — | [DATA_NEEDED: process technology] |
| DSP Blocks | — | [DATA_NEEDED: DSP block count] |
| PLL Count | — | [DATA_NEEDED: PLL count] |
| Configuration Method | — | Passive serial / Fast passive parallel / JTAG |