EP1S10B672C7N vs EP1S10B672C6 Perbandingan

Perbandingan bersamaan detil EP1S10B672C7N dari Intel dan EP1S10B672C6 dari Intel. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.

Perbandingan Spesifikasi

Parameter Umum EP1S10B672C7N EP1S10B672C6
Merek Intel Intel
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup NRND Obsolete
Manufacturer Intel / Altera Intel / Altera
Product Family Stratix —
Logic Family CMOS CMOS
Logic Elements/Cells 10570 cells —
Maximum Internal Clock 420.17 MHz —
Core Supply Voltage 1.5 V —
Technology Node 130 nm —
Package Code BGA —
Number of Terminals 672 —
Package Body Size 35 x 35 mm —
Ball Pitch 1.27 mm —
Package Shape Square —
Temperature Grade Commercial extended, 0 to 85 C —
Terminal Form Ball —
Configuration/JTAG JTAG boundary-scan per Stratix family data sheet —
Number of User I/O in 672-BGA [DATA_NEEDED: user I/O count] —
Total RAM Bits [DATA_NEEDED: total RAM bits] —
Embedded PLLs [DATA_NEEDED: PLL count] —
Config Device Compatibility [DATA_NEEDED: supported configuration devices] —
RoHS unknown - N suffix may indicate Pb-free, not verified in fetched data —
Series — Stratix
Logic Elements / Cells — 10,570
LABs / CLBs — 1,057
User I/Os — 345
Paket — 672-BBGA (35 x 35 mm, 1.27 mm pitch)
Supply Voltage (Core) — 1.5 V (1.425 V - 1.575 V)
Process Technology — 130 nm CMOS
Maximum Operating Frequency — 450.05 MHz
Suhu Kerja — 0 C to 85 C (Commercial Extended)
Tipe Mounting — Surface Mount (BGA)
Supplier Device Package — 672-BGA
Memory — Embedded TriMatrix (MRAM/M4K) blocks
DSP Blocks — Yes, dedicated multiply-accumulate blocks
Clock Management — PLLs for clock synthesis
Configuration — JTAG / passive serial / fast passive parallel
Status RoHS — Compliant

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