EP1S10B672C7N vs EP1S10F672C7N Perbandingan

Perbandingan bersamaan detil EP1S10B672C7N dari Intel dan EP1S10F672C7N dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.

Perbandingan Spesifikasi

Parameter Umum EP1S10B672C7N EP1S10F672C7N
Merek Intel Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup NRND Obsolete
Manufacturer Intel / Altera —
Product Family Stratix —
Logic Family CMOS —
Logic Elements/Cells 10570 cells —
Maximum Internal Clock 420.17 MHz —
Core Supply Voltage 1.5 V —
Technology Node 130 nm —
Package Code BGA —
Number of Terminals 672 —
Package Body Size 35 x 35 mm —
Ball Pitch 1.27 mm —
Package Shape Square —
Temperature Grade Commercial extended, 0 to 85 C —
Terminal Form Ball —
Configuration/JTAG JTAG boundary-scan per Stratix family data sheet —
Number of User I/O in 672-BGA [DATA_NEEDED: user I/O count] —
Total RAM Bits [DATA_NEEDED: total RAM bits] 920,448
Embedded PLLs [DATA_NEEDED: PLL count] —
Config Device Compatibility [DATA_NEEDED: supported configuration devices] —
RoHS unknown - N suffix may indicate Pb-free, not verified in fetched data —
Series — Stratix
Logic Elements / Cells — 10,570
Number of LABs/CLBs — 1,057
Number of User I/Os — 345
Number of Gates — [DATA_NEEDED: total gate count]
DSP Blocks — 6
Package Type — 672-BBGA (FBGA) 35 x 35 mm, 1.27 mm pitch
Tipe Mounting — Surface Mount
Process Technology — 130 nm CMOS
Core Voltage — 1.5 V
Maximum Operating Frequency — 420.17 MHz
Suhu Kerja — 0C to +85C (Commercial)
Configuration Method — SRAM, JTAG, passive/active serial/parallel
Status RoHS — [DATA_NEEDED: RoHS compliance]
Level MSL — [DATA_NEEDED: MSL moisture sensitivity level]

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