EP1S20F672C7N vs EP1S25F672C7N Perbandingan

Perbandingan bersamaan detil EP1S20F672C7N dari Intel dan EP1S25F672C7N dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.

Perbandingan Spesifikasi

Parameter Umum EP1S20F672C7N EP1S25F672C7N
Merek Intel Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete Obsolete
Series Stratix (first generation) —
Family Stratix —
Logic Elements (LEs) 18,460 25,660
Logic Cells 18,460 —
Configurable Logic Blocks (CLBs) 2,132 —
Embedded Memory (TriMatrix) 1,669,248 bits (426 Kbit total) —
DSP Blocks 56 (dedicated 18x18 multipliers) —
Maximum User I/O 586 473
I/O Banks [DATA_NEEDED: I/O bank count] —
PLLs Up to 12 —
Maximum Operating Frequency 420.17 MHz —
Core Voltage 1.5 V —
Process Technology 130 nm CMOS 0.13 µm CMOS
Paket 672-FBGA (FineLine BGA) 672-BBGA (FineLine BGA), 35 × 35 mm, 1.27 mm pitch
Package Body Size 35 mm x 35 mm —
Ball Pitch 1.27 mm —
Suhu Kerja 0°C to +85°C (commercial) 0 °C to 85 °C (commercial)
Speed Grade C7 (-7) —
Tipe Mounting Surface Mount Surface Mount
Lead-Free / RoHS Yes (lead-free finish, RoHS compliant) —
Configuration Modes PS, PPS, FPP, JTAG —
Level MSL [DATA_NEEDED: moisture sensitivity level] [DATA_NEEDED: MSL rating]
Device Family — Stratix
Logic Array Blocks (LABs) — 2,566
Embedded Memory Bits — 1,944,576
Number of I/O Pins — 672 (BGA balls)
Core Supply Voltage (VCCINT) — 1.5 V
I/O Supply Voltage (VCCIO) — [DATA_NEEDED: bank-dependent 1.2 V–3.3 V]
Configuration Method — JTAG / Passive Serial / Active Serial
Status RoHS — [DATA_NEEDED: confirm from product page]

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