EP20K200EBC356-1 vs EP20K200CB356C8N Perbandingan

Perbandingan bersamaan detil EP20K200EBC356-1 dari Altera dan EP20K200CB356C8N dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.

Perbandingan Spesifikasi

Parameter Umum EP20K200EBC356-1 EP20K200CB356C8N
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete Obsolete
Family APEX 20K (APEX 20KE) APEX 20KC
System Gates 200,000 200,000
Logic Elements / Cells 8,320 —
Maximum User I/Os 277 —
Core Voltage 1.8 V (1.71 V to 1.89 V) —
Process Technology 0.22 µm CMOS 0.15 um CMOS
Propagation Delay 2.5 ns —
Internal Performance Up to 367 MHz —
Paket 356-ball LBGA (35 x 35 mm) 356-ball LBGA
Tipe Mounting Surface Mount (BGA) —
Suhu Kerja 0 °C to 85 °C (Commercial) —
Architecture MultiCore (LUT + product-term + embedded memory) —
On-chip Memory Embedded System Blocks (ESB / SRAM) —
Configuration Method JTAG (ByteBlaster / MasterBlaster), passive serial —
Development Software Altera Quartus II —
Status RoHS [DATA_NEEDED: RoHS status not stated in verified sources] [DATA_NEEDED: RoHS compliance]
Status Lingkungan Hidup Obsolete / EOL —
Series — EP20K200
Device Type — SRAM-based LUT FPGA
Logic Elements (Cells) — 8,320
Maximum Internal Frequency — 301.21 MHz
Propagation Delay (tpd) — 1.78 ns
Nominal Core Supply Voltage — 1.8 V
Core Supply Voltage Range — 1.71 V to 1.89 V
Number of User I/O Pins — 263
Number of Dedicated Inputs — 4
Total Macrocells / Output Functions — 263
Embedded Memory Bits — 106,496 bits
Number of PLLs — 4
MultiVolt I/O Support — 1.5 V / 1.8 V / 2.5 V / 3.3 V
Differential Signaling — LVDS
Configuration Interface — Serial / JTAG (IEEE 1149.1)
Operating Temperature (commercial "C") — 0 C to +85 C (TJ)
Terminal Finish ("N") — Lead-free / Pb-free
Tingkat Sensitivitas Kekeringan (MSL) — [DATA_NEEDED: MSL rating]

Spek dan Sumber

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