EP20K400CF672C8AA vs EP20K400CF672C7N Perbandingan
Perbandingan bersamaan detil EP20K400CF672C8AA dari Intel dan EP20K400CF672C7N dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.
Perbandingan Spesifikasi
| Parameter Umum | EP20K400CF672C8AA | EP20K400CF672C7N |
|---|---|---|
| Merek | Intel | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Obsolete |
| Family | APEX 20K | APEX 20KC |
| Number of Logic Elements/Cells | 16640 | — |
| Number of Logic Units (LEs) | [DATA_NEEDED: number of LUs] | — |
| Embedded System Blocks (ESBs) | 212 | — |
| On-chip RAM Bits | [DATA_NEEDED: total embedded memory bits] | — |
| Number of User I/O Pins | 488 | — |
| Package Type | 672-ball Fine-Pitch BGA (FBGA) | — |
| Number of Pins/Balls | 672 | — |
| Supply Voltage (Core) | 2.5 V | — |
| I/O Standards Supported | LVTTL, LVCMOS, PCI, SSTL, HSTL (multi-voltage I/O) | — |
| Propagation Delay | [DATA_NEEDED: typical propagation delay] | 2.5 ns (catalog) / 1.48 ns (some catalog) |
| Suhu Kerja | 0 C to 85 C (Commercial) | 0 C to 85 C (Commercial) |
| Tipe Mounting | Surface Mount | Surface Mount (BGA) |
| Packaging | Tray | — |
| Tingkat Sensitivitas Kekeringan (MSL) | 3 (168 Hours) | — |
| Configuration Interface | JTAG (IEEE 1149.1), passive serial, passive parallel asynchronous | — |
| Status RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status not in provided data] |
| Maximum System Gates | — | 1,052,000 |
| Typical Gates | — | 400,000 |
| Logic Elements (LEs) | — | 16,640 |
| Embedded Memory | — | 488 Kbits |
| Maximum User I/O | — | 488 |
| User I/O (per catalog) | — | 480 / 502 (per source) |
| Paket | — | 672-ball FineLine BGA (FC-FBGA / BBGA) |
| Process Technology | — | 0.18-micron CMOS, all-layer copper interconnect |
| Core Voltage (VCCINT) | — | 1.8 V |
| I/O Voltage (VCCIO) | — | 3.3 V / 2.5 V banked |
| Maximum Frequency | — | 375.94 MHz (internal) |
| Level MSL | — | 3 (per JEDEC J-STD-020) |
| Configuration Modes | — | PS, PPS, JTAG |