EP2A25F672I8 vs EP2A25F672C7 Perbandingan
Perbandingan bersamaan detil EP2A25F672I8 dari Altera dan EP2A25F672C7 dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.
Perbandingan Spesifikasi
| Parameter Umum | EP2A25F672I8 | EP2A25F672C7 |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | NRND |
| Family | APEX II | — |
| Logic Elements / Cells | 24,320 | — |
| Equivalent Gates | 900,000 | — |
| Embedded Memory (RAM bits) | 622,592 | — |
| User I/Os | 492 | — |
| Number of PLLs | 4 | — |
| Process Technology | 0.15 µm CMOS, up to 8 metal layers | 0.15-um all-layer copper, up to 8 metal layers |
| Core Supply Voltage | 1.5 V | — |
| Propagation Delay | 1.69 ns (typical) | — |
| Internal Performance | 333 MHz (per legacy datasheet) | — |
| LVDS / High-Speed I/O | Yes, up to 1 Gbps | — |
| Paket | 672-ball FC-FBGA (FineLine BGA), 27 × 27 mm, 1 mm pitch | 672-ball FCBGA (FineLine BGA) |
| Tipe Mounting | Surface Mount (BGA) | — |
| Suhu Kerja | –40 °C to +85 °C (industrial, 'I' grade) | 0C to +85C (Commercial) |
| Speed Grade | I8 (industrial, 8-speed-grade per APEX II ordering scheme) | -7 |
| JTAG / Boundary Scan | IEEE 1149.1 compliant | — |
| I/O Standards Supported | LVTTL, LVCMOS, SSTL, HSTL, LVDS, LVPECL, GTL+, PCI | LVDS, LVPECL, PCML, HyperTransport |
| Status RoHS | unknown | [DATA_NEEDED: RoHS status] |
| Lead-Free Status | unknown | — |
| Product Family | — | APEX II |
| Logic Elements | — | 25,000 |
| Maximum System Gates | — | 1,650,000 |
| Maximum RAM Bits | — | 422,976 |
| User I/O Count | — | 492 |
| Supply Voltage (Core) | — | 1.5 V |
| LVDS Data Rate | — | 1 Gbps per channel (True-LVDS) |
| Configuration Mode | — | Passive Serial, Passive Parallel, JTAG |
| Embedded System Blocks (ESB) | — | Yes - RAM, ROM, CAM, multiplier support |