EP910DC-35 vs EP910DC-30 Perbandingan
Perbandingan bersamaan detil EP910DC-35 dari Altera dan EP910DC-30 dari Intel. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.
Perbandingan Spesifikasi
| Parameter Umum | EP910DC-35 | EP910DC-30 |
|---|---|---|
| Merek | Altera | Intel |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Obsolete |
| Device Type | UV-Erasable CMOS PLD (PAL-type) | — |
| Family | Classic EPLD EP910 | Classic EPLD (EP910 series) |
| Architecture | PAL-type sum-of-products AND-OR array | PAL-type AND-OR sum-of-products, CMOS |
| Usable Gates | 900 gates | — |
| Macrocells | 24 | 24 |
| Product Terms | 240 | — |
| Dedicated Inputs | 12 | 36 |
| I/O Pins | 24 | — |
| Total Inputs | 36 | — |
| Propagation Delay (tpd) | 35 ns | — |
| Frekuensi Bawah Maximum | 37 MHz (typical, internal) | — |
| Supply Voltage (Vcc) | 4.75 V to 5.25 V (5 V nominal) | — |
| Suhu Kerja | 0 °C to +70 °C (commercial) | 0C to +70C (commercial) |
| Paket | 40-pin CDIP (Ceramic DIP) with quartz window | DIP-40 (through-hole, 600 mil) |
| Lead Pitch | 2.540 mm | — |
| Termination Style | Through-Hole | — |
| Programming Method | JEDEC fuse map via device programmer; UV erase | UV-Erasable / OTP |
| Technology | CMOS, UV-erasable EPROM cell | — |
| Status RoHS | Non-compliant (ceramic DIP with Pb-bearing lead finish) | — |
| Lifecycle | Obsolete / last-time-buy from authorized distributors | — |
| Gate Count | — | 900 usable gates |
| Propagation Delay (tPD) | — | 30 ns (max) |
| Clock Frequency (fCNT) | — | 33.3 MHz |
| Outputs (Macrocells) | — | 24 |
| External Clock Pins | — | 2 (CLK1, CLK2) |
| Tegangan Pemuat | — | 5 V |
| Process Technology | — | CMOS |
| Tipe Mounting | — | Through-Hole |