EP910LC-35 vs EP910LC-32 Perbandingan

Perbandingan bersamaan detil EP910LC-35 dari Altera dan EP910LC-32 dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.

Perbandingan Spesifikasi

Parameter Umum EP910LC-35 EP910LC-32
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete Obsolete
Product Type EPLD (Erasable Programmable Logic Device) —
Family Classic (EP910) —
Macrocells 24 —
Usable Gates 450 —
Propagation Delay (tPD) 35 ns —
Maximum Toggle Frequency 28.6 MHz —
Supply Voltage (VCC) 5 V 5 V
Technology CMOS EPROM —
Paket PLCC-44 (J-lead, LC suffix) PLCC-32
Suhu Kerja 0C to +70C (commercial) —
Jumlah Pin 44 —
Programmable Flip-Flops Yes (per macrocell) —
Output Enable Control Per macrocell —
Erasure Method UV (windowed) or OTP (plastic) —
Status RoHS Not applicable (legacy product) unknown
Device Family — Altera Classic EPLD
Number of Macrocells — 24
Number of Usable Gates — 900 gates (typical)
Number of Dedicated Inputs — 10
Number of I/O Pins — 20
Speed Grade — -32
Maximum Toggle Frequency (fMAX) — [DATA_NEEDED: fMAX value in MHz for -32 grade]
Pin-to-Pin Propagation Delay (tPD) — [DATA_NEEDED: tPD in ns for -32 grade]
Logic Family — Low-power CMOS (LC suffix)
Programming Method — UV-erasable or one-time programmable (OTP for LC windowless variant)
Rentang Suhu Kerja — [DATA_NEEDED: commercial or industrial grade]
I/O Standard — TTL-compatible
Tipe Mounting — Surface Mount (PLCC socket or direct solder)
Level MSL — unknown

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