EP910LI-35BF vs EP910LC44-35 Perbandingan
Perbandingan bersamaan detil EP910LI-35BF dari Altera dan EP910LC44-35 dari Intel. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.
Perbandingan Spesifikasi
| Parameter Umum | EP910LI-35BF | EP910LC44-35 |
|---|---|---|
| Merek | Altera | Intel |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | NRND |
| Device Family | Altera Classic EPLD | — |
| Part Number Base | EP910 | — |
| Logic Density | 450 usable gates | — |
| Macrocells | 24 | 24 |
| Maximum Pin-to-Pin Delay (tpd) | 35 ns | — |
| Maximum Toggle Frequency (fmax) | 28.6 MHz | — |
| Supply Voltage (VCC) | 5 V (nominal) | 5 V (single supply) |
| Paket | 44-pin PLCC (J-lead) | 44-pin PLCC (J-leaded) |
| Rentang Suhu Kerja | Industrial (LI suffix) | — |
| Technology | CMOS, UV-erasable | — |
| Programming Method | EPROM/UV-erase programmer (Altera Classic algorithm) | — |
| Output Polarity Control | Programmable XOR per macrocell | — |
| Flip-Flop Type | Selectable D/T/JK/SR per macrocell | — |
| TTL Compatibility | 100% TTL emulation | — |
| Compliance / EOL Status | Obsolete - last-time buy exhausted; second-source via Rochester Electronics | — |
| Family | — | Classic EPLD (OT sub-family) |
| Architecture | — | PAL-type AND/OR array |
| Usable Gates | — | 450 |
| Propagation Delay (tPD) | — | 35 ns (max) |
| Maximum Frequency (fMAX) | — | 28.6 MHz |
| Total Inputs | — | 36 |
| I/O Pins | — | 24 |
| Global Clocks | — | 2 |
| Suhu Kerja | — | 0C to +70C (commercial) |
| Tipe Mounting | — | Surface Mount |
| Process Technology | — | CMOS |
| Programmability | — | UV-erasable (windowed ceramic) |