EP910LI-35BF vs EP910LC44-35 比較
詳細並排比較 EP910LI-35BF 由 Altera 與 EP910LC44-35 由 Intel. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP910LI-35BF | EP910LC44-35 |
|---|---|---|
| 品牌 | Altera | Intel |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | NRND |
| Device Family | Altera Classic EPLD | — |
| Part Number Base | EP910 | — |
| Logic Density | 450 usable gates | — |
| Macrocells | 24 | 24 |
| Maximum Pin-to-Pin Delay (tpd) | 35 ns | — |
| Maximum Toggle Frequency (fmax) | 28.6 MHz | — |
| Supply Voltage (VCC) | 5 V (nominal) | 5 V (single supply) |
| 封裝 | 44-pin PLCC (J-lead) | 44-pin PLCC (J-leaded) |
| 工作溫度範圍 | Industrial (LI suffix) | — |
| Technology | CMOS, UV-erasable | — |
| Programming Method | EPROM/UV-erase programmer (Altera Classic algorithm) | — |
| Output Polarity Control | Programmable XOR per macrocell | — |
| Flip-Flop Type | Selectable D/T/JK/SR per macrocell | — |
| TTL Compatibility | 100% TTL emulation | — |
| Compliance / EOL Status | Obsolete - last-time buy exhausted; second-source via Rochester Electronics | — |
| Family | — | Classic EPLD (OT sub-family) |
| Architecture | — | PAL-type AND/OR array |
| Usable Gates | — | 450 |
| Propagation Delay (tPD) | — | 35 ns (max) |
| Maximum Frequency (fMAX) | — | 28.6 MHz |
| Total Inputs | — | 36 |
| I/O Pins | — | 24 |
| Global Clocks | — | 2 |
| 工作溫度 | — | 0C to +70C (commercial) |
| 安裝類型 | — | Surface Mount |
| Process Technology | — | CMOS |
| Programmability | — | UV-erasable (windowed ceramic) |