EP910PI-15T vs EP910PI-30T Perbandingan
Perbandingan bersamaan detil EP910PI-15T dari Altera dan EP910PI-30T dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.
Perbandingan Spesifikasi
| Parameter Umum | EP910PI-15T | EP910PI-30T |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Obsolete |
| Product Type | Classic EPLD (Erasable Programmable Logic Device) | EPLD (Erasable Programmable Logic Device) |
| Family | Altera Classic EPLD (EP910 series) | Altera Classic EPLD |
| Macrocells | 24 | 24 |
| Dedicated Inputs | 12 | 10 |
| I/O Pins | 24 | — |
| Logic Blocks | 6 LABs of 4 macrocells each (Classic architecture) | — |
| Tegangan Pemuat | 4.5 V to 5.5 V (5 V nominal) | — |
| Propagation Delay (tPD) | 15 ns max (speed grade -15) | 30 ns |
| Technology | CMOS EEPROM (electrically erasable) | CMOS, UV-erasable (windowed ceramic) |
| Paket | 40-pin PDIP (Plastic DIP, R-PDIP-T40) | — |
| Tipe Mounting | Through-Hole | Through-Hole |
| Output Drive Current | [DATA_NEEDED: per-pin DC output current, mA] | — |
| Suhu Kerja | [DATA_NEEDED: industrial/commercial temp range] | -40 C to +85 C (industrial) |
| Programming | JEDEC-standard, serial/parallel programmer | Altera Classic device programmer / MAX+PLUS II flow |
| Status RoHS | [DATA_NEEDED: original Altera part; likely non-RoHS as 5V PDIP] | [DATA_NEEDED: RoHS status] |
| Usable Gates | — | 480 |
| Register (Clock-to-Output) Delay | — | 20 ns |
| Supply Voltage (VCC) | — | 4.75 V to 5.25 V (5 V nominal) |
| Package Type | — | 40-pin PDIP (ceramic windowed) |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |