EP910PI-25 vs EP910PI-40 Perbandingan

Perbandingan bersamaan detil EP910PI-25 dari Intel dan EP910PI-40 dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.

Altera
EP910PI-40 EP910PI-40 - 24-Macrocell Classic EPLD, 43ns, PDIP-40 | Altera

EP910PI-40 - 24-Macrocell Classic EPLD, 43ns, PDIP-40 | Altera

EP910PI-40 ⚠ Waktu Beli Terakhir

Perbandingan Spesifikasi

Parameter Umum EP910PI-25 EP910PI-40
Merek Intel Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete Waktu Pembelian Terakhir
Family Altera Classic EPLD —
Device EP910 —
Macrocells 24 —
Dedicated Inputs 12 —
I/O Pins 24 —
Pin-to-Pin Propagation Delay (tPD) 25 ns —
Maximum Clock Frequency (fMAX) 40 MHz —
Supply Voltage (VCC) 5 V nominal 4.75 V to 5.25 V (5 V nominal)
Process Technology 5 V CMOS (EPROM-based) CMOS (UV-erasable)
Paket PDIP-40 (Plastic DIP) PDIP-40 (Plastic DIP, 40-pin)
Jumlah Pin 40 —
Tipe Mounting Through-Hole Through-Hole
Suhu Kerja 0C to +70C (commercial) 0C to +70C (commercial)
Programmability UV-erasable (windowed) / one-time-programmable —
Status RoHS Non-compliant (PDIP package) [DATA_NEEDED: RoHS compliance status]
Device Family — Classic EPLD
Part Number — EP910PI-40
Architecture — PAL-type macrocell, CMOS, UV-erasable
Number of Macrocells — 24
Number of Dedicated Inputs — 12
Number of I/O Lines — 24
External Clock Inputs — 2
Frekuensi Bawah Maximum — 25 MHz
Propagation Delay (tPD) — 43 ns
Speed Grade — -40 (43 ns)
Programming Method — UV-erase + Altera programmer (legacy)
Programmable Polarity — Yes (user-configurable output)
Output Enable Control — Yes (per-pin three-state)

Spek dan Sumber

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