EP910PI-25 vs EP910PI-40 比較
詳細並排比較 EP910PI-25 由 Intel 與 EP910PI-40 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EP910PI-25 | EP910PI-40 |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | 最後購買 |
| Family | Altera Classic EPLD | — |
| Device | EP910 | — |
| Macrocells | 24 | — |
| Dedicated Inputs | 12 | — |
| I/O Pins | 24 | — |
| Pin-to-Pin Propagation Delay (tPD) | 25 ns | — |
| Maximum Clock Frequency (fMAX) | 40 MHz | — |
| Supply Voltage (VCC) | 5 V nominal | 4.75 V to 5.25 V (5 V nominal) |
| Process Technology | 5 V CMOS (EPROM-based) | CMOS (UV-erasable) |
| 封裝 | PDIP-40 (Plastic DIP) | PDIP-40 (Plastic DIP, 40-pin) |
| 腳位數 | 40 | — |
| 安裝類型 | Through-Hole | Through-Hole |
| 工作溫度 | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Programmability | UV-erasable (windowed) / one-time-programmable | — |
| RoHS 狀態 | Non-compliant (PDIP package) | [DATA_NEEDED: RoHS compliance status] |
| Device Family | — | Classic EPLD |
| Part Number | — | EP910PI-40 |
| Architecture | — | PAL-type macrocell, CMOS, UV-erasable |
| Number of Macrocells | — | 24 |
| Number of Dedicated Inputs | — | 12 |
| Number of I/O Lines | — | 24 |
| External Clock Inputs | — | 2 |
| 最大時脈頻率 | — | 25 MHz |
| Propagation Delay (tPD) | — | 43 ns |
| Speed Grade | — | -40 (43 ns) |
| Programming Method | — | UV-erase + Altera programmer (legacy) |
| Programmable Polarity | — | Yes (user-configurable output) |
| Output Enable Control | — | Yes (per-pin three-state) |