EPC144LC20 vs EPC1LC20U Perbandingan
Perbandingan bersamaan detil EPC144LC20 dari Intel dan EPC1LC20U dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.
Intel
EPC144LC20 - 144KB Serial Config PROM, 20-LCC | Intel (Altera)
EPC144LC20 ⚠ Waktu Beli Terakhir
Perbandingan Spesifikasi
| Parameter Umum | EPC144LC20 | EPC1LC20U |
|---|---|---|
| Merek | Intel | Altera |
| Kategori | FPGA & CPLD | Memory ICs |
| Status Lingkungan Hidup | Waktu Pembelian Terakhir | Obsolete |
| Memory Capacity | 144 Kbit | — |
| Memory Organization | Serial (one-time programmable) | — |
| Tipe Antarmuka | Altera Serial Configuration (DATA, DCLK, nCONFIG, nSTATUS, CONF_DONE) | — |
| Programming Method | In-system via JTAG (IEEE 1149.1 / ByteBlaster / USB-Blaster) | Altera APU / third-party JTAG programmer |
| Supply Voltage (VCC) | 3.0 V to 5.5 V | — |
| Suhu Kerja | -40C to +85C (industrial) | [DATA_NEEDED: industrial/commercial grade range] |
| Configuration Time (typical) | [DATA_NEEDED: configuration time at DCLK = 10 MHz] | — |
| Active Supply Current | [DATA_NEEDED: ICC active] | — |
| Standby Supply Current | [DATA_NEEDED: ICC standby] | — |
| Paket | 20-pin LCC (Leadless Chip Carrier, JLCC-20) | 20-pin PLCC (9x9 mm) |
| Jumlah Pin | 20 | — |
| Tipe Mounting | Surface Mount | Surface Mount |
| Supported FPGA Families | Altera FLEX 6000 / 8000 / 10K, ACEX 1K, MAX 3000 / 7000, APEX 20K | — |
| Level MSL | 3 (168 hours) | [DATA_NEEDED] |
| Status RoHS | [DATA_NEEDED: RoHS compliance status per Intel PCN] | Compliant (Pb-free finish, "U" suffix) |
| Lead-Free | Yes | — |
| Bebas Halogen | [DATA_NEEDED] | — |
| JTAG Compliance | IEEE Std 1149.1 | — |
| Tipe Memori | — | OTP (One-Time-Programmable) Configuration PROM |
| Memory Density | — | 1 Mbit |
| Configuration Interface | — | Altera Serial Configuration (4-wire) |
| Maximum DCLK Frequency | — | 8 MHz |
| Operating Voltage (VCC) | — | 3.3 V typical [DATA_NEEDED: full range] |
| Configuration Time | — | [DATA_NEEDED: depends on bitstream length and DCLK] |
| Cascading Support | — | Yes (multi-PROM daisy-chain for larger bitstreams) |
| Lead-Free (Pb-free) Finish | — | Yes ("U" suffix) |
| Compatibility | — | Altera SRAM-based LUT FPGAs (APEX, FLEX, ACEX, Cyclone, Stratix families) |