EPC16SI16N vs EPC16QC100N Perbandingan
Perbandingan bersamaan detil EPC16SI16N dari Intel dan EPC16QC100N dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.
Intel
EPC16SI16N - 16Mb Enhanced Configuration Device, 16-SOIC | Altera / Intel
EPC16SI16N ⚠ Waktu Beli Terakhir
Perbandingan Spesifikasi
| Parameter Umum | EPC16SI16N | EPC16QC100N |
|---|---|---|
| Merek | Intel | Altera |
| Kategori | FPGA & CPLD | Memory ICs |
| Status Lingkungan Hidup | Waktu Pembelian Terakhir | Obsolete |
| Tipe Memori | Non-volatile flash (enhanced configuration device) | — |
| Ukuran Memori | 16 Mb (16,777,216 bits) | 16 Mbit (16,777,216 bits) |
| Antarmuka | Altera enhanced serial configuration (DCLK, DATA, nCS, nRESET, nSTATUS) | — |
| Programming Interface | JTAG (IEEE 1149.1 boundary scan) | — |
| Maximum Operating Frequency | 40 MHz (fast configuration mode) | — |
| Tegangan Pemuat Kerja | 3.3 V (typ) | — |
| Suhu Kerja | -40 C to +85 C (industrial, 'SI' suffix) | 0 C to 70 C |
| Paket | 16-pin SOIC (300 mil, 'SI' suffix) | 100-pin PQFP (20 x 14 mm) |
| Tipe Mounting | Surface Mount | Surface Mount |
| Lead-Free / Finish | Lead-free (matte tin), 'N' suffix | — |
| Level MSL | [DATA_NEEDED: MSL level] | — |
| Status RoHS | Compliant | — |
| In-System Programmability | Yes (via JTAG, multiple reprogramming cycles) | — |
| Compatible FPGA Series | Altera Stratix II, Stratix III, Cyclone, Cyclone II, Cyclone III | — |
| Configuration Daisy-Chaining | Supported (multiple devices / multiple FPGAs) | — |
| On-Chip Charge Pump | Integrated (no external VPP required) | — |
| Programmable Type | — | In System Programmable |
| Configuration Clock Frequency | — | 33 MHz max |
| On-Chip Decompression | — | Yes (supports compressed bitstreams) |
| Supply Voltage (VCC) | — | 3.0 V to 3.6 V |
| Access Time | — | 90 ns typical |
| Flash Read Bandwidth | — | 160 Mbps (16-bit DQ at 10 MHz) |
| Configuration Interface | — | FPP / PS / AS via dedicated FPGA pins |
| JTAG (IEEE 1149.1) ISP | — | Supported |
| Lead Free | — | Yes (per datasheet) |
| Packaging | — | Tray |
| Supported FPGA Families | — | ACEX 1K, APEX 20K, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, Mercury, Stratix, Stratix GX, Stratix II, Stratix II GX |