EPC1LC20-WCEC52 vs EPC1L120 Perbandingan
Perbandingan bersamaan detil EPC1LC20-WCEC52 dari Altera dan EPC1L120 dari Intel. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.
Intel
EPC1L120 - Altera/Intel Configuration Device 120 kbit Serial | PLCC-20
EPC1L120 ⚠ Waktu Beli TerakhirPerbandingan Spesifikasi
| Parameter Umum | EPC1LC20-WCEC52 | EPC1L120 |
|---|---|---|
| Merek | Altera | Intel |
| Kategori | Memory ICs | Memory ICs |
| Status Lingkungan Hidup | Obsolete | Waktu Pembelian Terakhir |
| Tipe Memori | OTP Configuration PROM (Anti-fuse) | Configuration EEPROM |
| Ukuran Memori | 1 Mbit (1,048,576 bits) | — |
| Organisasi | 212,942 x 1 bit | — |
| Antarmuka | Serial (Altera FPP/PS configuration protocol) | — |
| Configuration Clock (DCLK) | 8 MHz maximum | — |
| Supply Voltage (VCC) | 3.3 V | — |
| I/O Voltage Tolerance | 5.0 V (FPGA interface) | — |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | — |
| Programmability | One-Time Programmable (OTP) | In-System via JTAG (IEEE 1149.1) |
| Suhu Kerja | -40C to +85C (industrial) | -40C to +85C (industrial) |
| Paket | 20-pin PLCC (J-lead, through-hole, 9x9 mm) | PLCC-20 |
| Package Mounting | Through-hole (also accepts PLCC socket) | — |
| Status RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Compatible FPGA Families | Cyclone, Stratix, APEX, ACEX, MAX series | — |
| Programming Interface | JTAG (IEEE Std 1149.1) ISP | — |
| Jumlah Pin | 20 | — |
| Status Lingkungan Hidup | Obsolete (recommended replacement: EPCQ family or newer serial config devices) | — |
| Memory Capacity | — | 120 kbit |
| Tipe Antarmuka | — | Serial (Altera configuration protocol) |
| Tegangan Pemuat Kerja | — | 3.3 V / 5 V |
| Output Compatibility | — | MultiVolt: 1.5 V, 1.8 V, 2.5 V, 3.3 V, 5 V |
| JTAG Support | — | Yes (dedicated JTAG port) |
| Tipe Mounting | — | Surface Mount / Through-Hole (socket) |
| Reprogram Cycles | — | 100 cycles typical |
| Compatible Altera FPGAs | — | FLEX 6000, FLEX 8000, MAX 7000, MAX 9000 families |
| Cascade Support | — | Yes (multi-FPGA configuration chains) |
| Level MSL | — | [DATA_NEEDED: MSL level] |