EPC2LI20J vs EPC2LC20 Perbandingan

Perbandingan bersamaan detil EPC2LI20J dari Altera dan EPC2LC20 dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.

Perbandingan Spesifikasi

Parameter Umum EPC2LI20J EPC2LC20
Merek Altera Altera
Kategori Memory ICs Memory ICs
Status Lingkungan Hidup Aktif NRND
Harga Unit (USD) — $7,20
Tipe Memori In-System Programmable Configuration PROM (flash) Non-volatile configuration PROM
Ukuran Memori 1,695,680 bits (1.6Mb) 1.6 Mbit
Organisasi 65,536 x 1-bit (serial interface) —
Antarmuka Altera 4-pin serial configuration (DATA, DCLK, nCS, nCONFIG) —
Target FPGAs APEX II, APEX 20K/20KC/20KE, Mercury, ACEX 1K, FLEX 6000/10KE/10KA —
Supply Voltage (VCCINT) 3.0 V to 3.6 V (3.3 V typical) —
I/O Voltage (VCCIO) 5.0 V or 3.3 V tolerant —
ISP Programming Interface JTAG (IEEE 1149.1) —
Cascade Support Yes (multi-device configuration chain) Yes - daisy-chain multiple EPC2 devices via JTAG for larger bitstreams
Internal Oscillator Yes (configures without external clock source) —
Paket 20-pin PLCC with J-leads (JEDEC MS-018) 20-pin PLCC (J-lead, 9x9 mm)
Suhu Kerja -40C to +85C (industrial) -40C to +85C (industrial) [DATA_NEEDED: exact grade from datasheet]
Programming Cycles [DATA_NEEDED: minimum endurance cycles] —
Status RoHS [DATA_NEEDED: RoHS compliance status] Non-Compliant (original Altera Pb-containing part)
Lead-Free [DATA_NEEDED: lead-free status] —
Configuration Clock (DCLK) Up to 33 MHz —
Configuration Interface — Serial (x1) to FPGA via DCLK/nCONFIG/nSTATUS/CONF_DONE
Programming Interface — IEEE 1149.1 (JTAG) ISP, 5.0-V and 3.3-V tolerant
Supply Voltage VCC — 3.0 V to 3.6 V (3.3-V operation)
ISP Voltage Range — 5.0 V or 3.3 V
Supported FPGA Families — ACEX 1K, APEX 20K/20KC/20KE, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, MAX 9000
Tipe Mounting — Surface Mount
Lead-Free Version — EPC2LC20N available as lead-free equivalent
Programming Support — Altera Programming Unit (APU), Quartus II, JTAG programmer
Boundary-Scan — IEEE 1149.1 compliant, 8-bit or 16-bit JTAG

Spek dan Sumber

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