EPC2LI20J vs EPC2LC20 비교
다음의 상세 나란히 비교: EPC2LI20J 제조: Altera 및 EPC2LC20 제조: Altera. 주요 사양, 전기적 파라미터, 패키징, 수명 주기 상태, 가격 및 재고를 비교하여 설계 요구 사항에 가장 적합한 부품을 결정하십시오.
사양 비교
| 파라미터 | EPC2LI20J | EPC2LC20 |
|---|---|---|
| 브랜드 | Altera | Altera |
| 카테고리 | Memory ICs | Memory ICs |
| 수명 주기 상태 | 활성 | NRND |
| 재고 상태 | In Stock | In Stock |
| 단가 (USD) | $9.75 | $7.20 |
| 메모리 유형 | In-System Programmable Configuration PROM (flash) | Non-volatile configuration PROM |
| 메모리 크기 | 1,695,680 bits (1.6Mb) | 1.6 Mbit |
| 메모리 구성 | 65,536 x 1-bit (serial interface) | — |
| 인터페이스 | Altera 4-pin serial configuration (DATA, DCLK, nCS, nCONFIG) | — |
| Target FPGAs | APEX II, APEX 20K/20KC/20KE, Mercury, ACEX 1K, FLEX 6000/10KE/10KA | — |
| Supply Voltage (VCCINT) | 3.0 V to 3.6 V (3.3 V typical) | — |
| I/O Voltage (VCCIO) | 5.0 V or 3.3 V tolerant | — |
| ISP Programming Interface | JTAG (IEEE 1149.1) | — |
| Cascade Support | Yes (multi-device configuration chain) | Yes - daisy-chain multiple EPC2 devices via JTAG for larger bitstreams |
| Internal Oscillator | Yes (configures without external clock source) | — |
| 패키지 | 20-pin PLCC with J-leads (JEDEC MS-018) | 20-pin PLCC (J-lead, 9x9 mm) |
| 동작 온도 | -40C to +85C (industrial) | -40C to +85C (industrial) [DATA_NEEDED: exact grade from datasheet] |
| Programming Cycles | [DATA_NEEDED: minimum endurance cycles] | — |
| RoHS 상태 | [DATA_NEEDED: RoHS compliance status] | Non-Compliant (original Altera Pb-containing part) |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Configuration Clock (DCLK) | Up to 33 MHz | — |
| Configuration Interface | — | Serial (x1) to FPGA via DCLK/nCONFIG/nSTATUS/CONF_DONE |
| Programming Interface | — | IEEE 1149.1 (JTAG) ISP, 5.0-V and 3.3-V tolerant |
| Supply Voltage VCC | — | 3.0 V to 3.6 V (3.3-V operation) |
| ISP Voltage Range | — | 5.0 V or 3.3 V |
| Supported FPGA Families | — | ACEX 1K, APEX 20K/20KC/20KE, APEX II, Arria GX, Cyclone, Cyclone II, FLEX 10K, FLEX 6000, MAX 9000 |
| 실장 유형 | — | Surface Mount |
| Lead-Free Version | — | EPC2LC20N available as lead-free equivalent |
| Programming Support | — | Altera Programming Unit (APU), Quartus II, JTAG programmer |
| Boundary-Scan | — | IEEE 1149.1 compliant, 8-bit or 16-bit JTAG |