EPC2LI20U vs EPC2LI20 Perbandingan
Perbandingan bersamaan detil EPC2LI20U dari Altera dan EPC2LI20 dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.
Perbandingan Spesifikasi
| Parameter Umum | EPC2LI20U | EPC2LI20 |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | Memory ICs | Memory ICs |
| Status Lingkungan Hidup | Obsolete | NRND |
| Tipe Memori | Configuration PROM (serial EEPROM) | Flash (in-system programmable) |
| Ukuran Memori | 1.6 Mbit (65,536 x 1-bit device) | 1.6 Mb (1,572,864 bits) |
| Supply Voltage (VCC) | 3.0 V to 5.5 V (5.0 V nominal) | — |
| Programming Voltage | 5.0 V (via internal charge pump) | — |
| Configuration Interface | Serial 4-pin (DATA, DCLK, nCS, OE) | Serial or Byte-wide (parallel) |
| Maximum DCLK Frequency | 33 MHz (fast mode) | — |
| Rentang Suhu Kerja | -40 C to +85 C (industrial) | — |
| Paket | 20-pin PLCC (9x9 mm) | — |
| Tipe Mounting | Surface Mount (PLCC socket) | Surface Mount (PLCC socket-compatible) |
| Programmability | In-system programmable via JTAG (IEEE 1149.1) | — |
| Cascade Support | Yes (via nCASC pin) | — |
| Device ID | 32-bit JTAG-readable | — |
| Supported FPGA Families | APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 6000/10KE/10KA | — |
| Status RoHS | [DATA_NEEDED: rohs status] | [DATA_NEEDED: RoHS status] |
| Level MSL | [DATA_NEEDED: MSL moisture sensitivity level] | [DATA_NEEDED: MSL level] |
| Programmable Type | — | In System Programmable (ISP) |
| Fungsi | — | Configuration PROM for SRAM-based FPGAs |
| Supply Voltage - Operating | — | 3.0 V to 3.6 V and 4.5 V to 5.5 V (auto-sensing) |
| Suhu Kerja | — | -40 C to +85 C (Industrial) |
| Paket / Case | — | 20-PLCC (J-lead, 9x9 mm) |
| Decompression | — | On-chip (supports compressed bitstreams) |
| JTAG / ISP Interface | — | IEEE 1532 (TCK, TMS, TDI, TDO) |
| Multi-Device Support | — | Yes (daisy-chain configuration) |
| User-Accessible Memory | — | Yes (unused flash available to user logic) |