EPC2LI20U vs EPC2LI20 比較

詳細並排比較 EPC2LI20U 由 Altera 與 EPC2LI20 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況,以找出最符合您設計需求的元件。

規格比較

參數 EPC2LI20U EPC2LI20
品牌 Altera Altera
類別 Memory ICs Memory ICs
生命週期狀態 Obsolete NRND
記憶體類型 Configuration PROM (serial EEPROM) Flash (in-system programmable)
記憶體容量 1.6 Mbit (65,536 x 1-bit device) 1.6 Mb (1,572,864 bits)
Supply Voltage (VCC) 3.0 V to 5.5 V (5.0 V nominal) —
Programming Voltage 5.0 V (via internal charge pump) —
Configuration Interface Serial 4-pin (DATA, DCLK, nCS, OE) Serial or Byte-wide (parallel)
Maximum DCLK Frequency 33 MHz (fast mode) —
工作溫度範圍 -40 C to +85 C (industrial) —
封裝 20-pin PLCC (9x9 mm) —
安裝類型 Surface Mount (PLCC socket) Surface Mount (PLCC socket-compatible)
Programmability In-system programmable via JTAG (IEEE 1149.1) —
Cascade Support Yes (via nCASC pin) —
Device ID 32-bit JTAG-readable —
Supported FPGA Families APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 6000/10KE/10KA —
RoHS 狀態 [DATA_NEEDED: rohs status] [DATA_NEEDED: RoHS status]
MSL 等級 [DATA_NEEDED: MSL moisture sensitivity level] [DATA_NEEDED: MSL level]
Programmable Type — In System Programmable (ISP)
功能 — Configuration PROM for SRAM-based FPGAs
Supply Voltage - Operating — 3.0 V to 3.6 V and 4.5 V to 5.5 V (auto-sensing)
工作溫度 — -40 C to +85 C (Industrial)
封裝 / 外殼 — 20-PLCC (J-lead, 9x9 mm)
Decompression — On-chip (supports compressed bitstreams)
JTAG / ISP Interface — IEEE 1532 (TCK, TMS, TDI, TDO)
Multi-Device Support — Yes (daisy-chain configuration)
User-Accessible Memory — Yes (unused flash available to user logic)

資料表與資源

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