EPC4QI1OON vs EPC4QI100N Perbandingan
Perbandingan bersamaan detil EPC4QI1OON dari Altera dan EPC4QI100N dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.
Altera
EPC4QI1OON - Altera Enhanced Configuration PROM 4Mb | 100-PQFP
EPC4QI1OON ⚠ Waktu Beli Terakhir
Perbandingan Spesifikasi
| Parameter Umum | EPC4QI1OON | EPC4QI100N |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | Memory ICs | Memory ICs |
| Status Lingkungan Hidup | Waktu Pembelian Terakhir | Aktif |
| Harga Unit (USD) | — | $10,40 |
| Manufacturer | Altera (now Intel) | — |
| Device Type | Enhanced Configuration PROM (Parallel Interface) | — |
| Ukuran Memori | 4 Mbit | 4 Mbit (4,194,304 bits) |
| Memory Width | 16-bit | — |
| Antarmuka | Altera Enhanced Configuration (parallel-style) | Altera serial (x1) configuration + JTAG |
| Paket | 100-pin PQFP (20 x 14 mm) | 100-pin PQFP (PowerPQFP, 20x14 mm) |
| Suhu Kerja | -40C to +85C (Industrial) | -40C to +85C (industrial) |
| Tegangan Pemuat | 3.3 V | — |
| In-System Programming | Yes (IEEE 1149.1 JTAG) | — |
| Tipe Mounting | Surface Mount | Surface Mount |
| Compatible FPGA Families | Stratix, Cyclone, APEX, Mercury, Excalibur | — |
| Configuration Mode | Master/slave via JTAG or EPC controller | — |
| Status RoHS | Compliant (verify per lot) | [DATA_NEEDED: RoHS compliance] |
| Lead-Free | Yes | — |
| Level MSL | [DATA_NEEDED: MSL rating] | [DATA_NEEDED: MSL rating] |
| Tipe Memori | — | In-System Programmable Configuration PROM (NOR flash) |
| Programmable Type | — | In System Programmable (ISP via JTAG) |
| Supply Voltage (VCC) | — | 3.0 V to 3.6 V |
| Configuration Clock DCLK | — | [DATA_NEEDED: DCLK maximum frequency] |
| Active Supply Current (ICC active) | — | [DATA_NEEDED: ICC active typical value] |
| Standby Supply Current | — | [DATA_NEEDED: ICC standby typical value] |
| Storage Temperature | — | -65C to +150C |
| Package Code | — | QI100 (PQFP-100, industrial) |
| JTAG Standard | — | IEEE 1149.1 boundary-scan / ISP |
| Cascading | — | Supported (multi-device daisy chain) |
| Target FPGAs | — | Altera Cyclone, Cyclone II, Stratix series |