EPM3064ATC100-7N vs EPM3064ATI100-10N Perbandingan

Perbandingan bersamaan detil EPM3064ATC100-7N dari Altera dan EPM3064ATI100-10N dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.

Perbandingan Spesifikasi

Parameter Umum EPM3064ATC100-7N EPM3064ATI100-10N
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup NRND Aktif
Family MAX 3000A MAX 3000A
Device Type CPLD - Complex Programmable Logic Device CPLD (Complex Programmable Logic Device)
Macrocells 64 64
Logic Array Blocks (LABs) 2 4
User I/O Pins 66 —
Usable Gates up to 1,250 1,250
Propagation Delay (tPD) 7.5 ns (pin-to-pin, -7 speed grade) —
Maximum Internal Frequency 166.7 MHz (-7 speed grade) 227.3 MHz (counter)
Core Supply Voltage (VCCINT) 3.3 V —
I/O Supply Voltage (VCCIO) 3.3 V or 2.5 V —
Program Memory Technology EEPROM (non-volatile) —
In-System Programming IEEE Std. 1149.1 (JTAG), IEEE Std. 1532 —
Paket TQFP-100 100-pin TQFP (industrial)
Tipe Mounting Surface Mount —
Suhu Kerja 0 °C to +70 °C (commercial) -40 C to +85 C (industrial)
Status RoHS [DATA_NEEDED: confirmed RoHS status from manufacturer page] RoHS Non-Compliant
Programmable Type — In-System Programmable (ISP) via IEEE 1149.1 JTAG
Technology — CMOS EEPROM
User I/O — 66
Supply Voltage (Core / I/O) — 3.3 V
Pin-to-Pin Delay (tPD) — 10 ns (-10 speed grade)
JTAG (IEEE 1149.1) — Yes
PCI Compliance — PCI Local Bus Specification Revision 2.2 (-4/-5/-6/-7/-10 speed grades)
MultiVolt I/O — Supports 2.5 V / 3.3 V / 5 V mixed-voltage interfacing
Lead-Free Status — Contains Lead

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