EPM3064ATC44-10NAF vs EPM3064ATC44-4N Perbandingan

Perbandingan bersamaan detil EPM3064ATC44-10NAF dari Altera dan EPM3064ATC44-4N dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.

Perbandingan Spesifikasi

Parameter Umum EPM3064ATC44-10NAF EPM3064ATC44-4N
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup NRND NRND
Series MAX 3000A —
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Macro Cells 64 64
Logic Elements / LABs 4 LABs (16 macrocells per LAB) —
Usable Gates 1250 1,250
Number of I/O Pins 34 —
Propagation Delay (tPD, max) 10 ns —
Supply Voltage (VCCINT) 3.0 V to 3.6 V 3.3 V
I/O Voltage Tolerance Multi-voltage (3.3 V / 2.5 V / 1.8 V capable) —
Programmable Technology EEPROM (non-volatile) —
In-System Programmable Yes (IEEE Std. 1532 compliant) —
Boundary-Scan Test Yes (IEEE Std. 1149.1 JTAG) —
Pin-Locking Yes —
Paket TQFP-44 (10x10 mm) 44-pin TQFP
Tipe Mounting Surface Mount Surface Mount
Suhu Kerja [DATA_NEEDED: industrial/commercial grade] 0C to +70C (commercial)
Lead Finish Lead-free (NiPdAu, AF suffix) —
Status RoHS Compliant [DATA_NEEDED: rohs status]
Configuration Memory Cycles 100 erase/program cycles —
Family — MAX 3000A
Logic Array Blocks — 2
Number of I/Os — 34
Dedicated Inputs — 4
Propagation Delay (tpd) — 4.5 ns
Maximum Counter Frequency — 222.2 MHz
I/O Supply Voltage (VCCIO) — 2.5 V or 3.3 V
Programmability — EEPROM, in-system programmable (JTAG)
JTAG Support — IEEE Std. 1149.1 (boundary-scan) and IEEE Std. 1532 (ISP)

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