EPM3256AQC208-10 vs EPM3256AQC208-10N Perbandingan
Perbandingan bersamaan detil EPM3256AQC208-10 dari Altera dan EPM3256AQC208-10N dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.
Altera
EPM3256AQC208-10 - MAX 3000A CPLD 256 Macrocells 10ns 208-PQFP | Intel / Altera
EPM3256AQC208-10 ObsoletePerbandingan Spesifikasi
| Parameter Umum | EPM3256AQC208-10 | EPM3256AQC208-10N |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Obsolete |
| Family | MAX 3000A | — |
| Logic Family | CMOS (EEPROM-based) | — |
| Macrocells | 256 | — |
| Usable Gates | 5,000 | 10,000 |
| User I/Os | 161 | — |
| Jumlah Pin | 208 | — |
| Paket | 208-BFQFP (PQFP, Gull Wing) | — |
| Pin-to-Pin Propagation Delay | 10 ns | — |
| Counter Frequency (max) | 227.3 MHz | — |
| Supply Voltage (VCCINT) | 3.3 V | — |
| I/O Tolerance | MultiVolt 2.5 V / 3.3 V / 5.0 V tolerant | 5 V tolerant, MultiVolt interface |
| Programming Interface | IEEE 1149.1 JTAG (ISP) | — |
| Suhu Kerja | 0 °C to +70 °C (Commercial) | 0C to +70C (Commercial) |
| PCI-SIG Compliance | Yes (speed grades -4, -5, -6, -7, -10) | — |
| Global Clock Networks | 4 (CLK, CLR, OE, GCLK) | — |
| Tipe Mounting | Surface Mount | Surface Mount |
| Status RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: lead-free status - non-RoHS suffix 'N' typically indicates lead-free finish, but datasheet not present in data] |
| Series | — | MAX 3000A |
| Programmable Type | — | In-System Programmable (EEPROM) |
| Number of Macrocells | — | 256 |
| Number of Logic Elements/Blocks | — | 16 LABs |
| Number of I/O Pins | — | 161 (158 user I/O per Arrow listing) |
| Propagation Delay (tpd) | — | 10 ns (max) |
| Maximum Counter Frequency | — | 227.3 MHz |
| Supply Voltage - Internal | — | 3.0 V to 3.6 V (3.3 V typical) |
| Paket / Case | — | 208-BFQFP / 208-PQFP (28x28 mm) |
| ISP Compliance | — | IEEE Std. 1532 |
| Boundary Scan | — | IEEE Std. 1149.1 (JTAG) |