EPM3256ATC144-7N vs EPM3256ATI144-7N Perbandingan

Perbandingan bersamaan detil EPM3256ATC144-7N dari Altera dan EPM3256ATI144-7N dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.

Altera
EPM3256ATC144-7N EPM3256ATC144-7N - MAX 3000A CPLD 256 Macro 7.5ns | Altera

EPM3256ATC144-7N - MAX 3000A CPLD 256 Macro 7.5ns | Altera

EPM3256ATC144-7N ⚠ Waktu Beli Terakhir

Perbandingan Spesifikasi

Parameter Umum EPM3256ATC144-7N EPM3256ATI144-7N
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Waktu Pembelian Terakhir Obsolete
Family MAX 3000A MAX 3000A
Device Type CPLD - Complex Programmable Logic Device CPLD (Complex Programmable Logic Device)
Macro Cells 256 —
Logic Gates (usable) 5,000 —
Number of Logic Array Blocks (LABs) 16 —
User I/Os 116 —
Propagation Delay (tPD) 7.5 ns 7.5 ns (typical)
Maximum Internal Frequency 126.6 MHz 126.6 MHz
Supply Voltage (VCCIO) 3.0 V to 3.6 V —
Programmable Logic Technology CMOS EEPROM-based —
In-System Programmable (ISP) Yes (3.3 V) —
Suhu Kerja 0C to +70C (Commercial) -40C to +85C (industrial)
Paket 144-pin TQFP TQFP-144 (20 x 20 mm, 0.5 mm pitch)
Tipe Mounting Surface Mount —
Logic Family CMOS —
JTAG Support IEEE 1149.1 boundary-scan —
Status RoHS Compliant Compliant (lead-free)
Macrocells — 256
Usable Gates — 5,000
Logic Array Blocks (LABs) — 16
Maximum User I/O Pins — 116
Core Supply Voltage (VCCINT) — 3.3 V
I/O Supply Voltage (VCCIO) — 3.3 V or 2.5 V
MultiVolt I/O Logic Levels — 5.0 V / 3.3 V / 2.5 V
Programming Technology — EEPROM (in-system programmable)
JTAG / ISP — IEEE Std. 1532 compliant
Boundary Scan — IEEE Std. 1149.1 (JTAG)
Hot-Socketing Support — Yes

Spek dan Sumber

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