EPM3512AFC256-2 vs EPM3512AFC256-10N Perbandingan

Perbandingan bersamaan detil EPM3512AFC256-2 dari Altera dan EPM3512AFC256-10N dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.

Perbandingan Spesifikasi

Parameter Umum EPM3512AFC256-2 EPM3512AFC256-10N
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete Obsolete
Family MAX 3000A MAX 3000A
Macrocells 512 512
Logic Array Blocks (LABs) 16 [DATA_NEEDED: number of LABs]
Maximum User I/O Pins 212 —
Propagation Delay (tPD, -2 grade) [DATA_NEEDED: tPD ns] —
Maximum Operating Frequency [DATA_NEEDED: fMAX MHz] —
Core Supply Voltage 3.3 V —
I/O Output Drive Voltage 2.5 V or 3.3 V (MultiVolt) —
Input Tolerance 2.5 V, 3.3 V, 5.0 V tolerant —
Paket BGA-256 (FineLine BGA) 256-ball FBGA (17 mm x 17 mm)
Ball Pitch 1.0 mm —
Programming Interface JTAG (IEEE Std 1149.1) / ByteBlaster —
Process Technology 0.30 um CMOS EEPROM —
Suhu Kerja 0C to +70C (commercial) —
Status RoHS [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status]
Speed Grade -2 —
Usable Gates — 10000
User I/O Pins — 208
Operating Frequency (fMAX) — [DATA_NEEDED: fMAX MHz]
Pin-to-Pin Delay (tPD) — 10 ns
Setup Time (tSU) — 4.5 ns
VCCINT (Core Supply) — 3.3 V
VCCIO (I/O Supply) — 3.3 V or 2.5 V
Technology — CMOS EEPROM-based, non-volatile
Operating Temperature (Commercial) — 0 C to +70 C
ISP Interface — IEEE Std. 1149.1 JTAG, IEEE Std. 1532
Tipe Mounting — Surface Mount (BGA)
Level MSL — [DATA_NEEDED: MSL rating]

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