EPM3512AQI20810 vs EPM3512AQC208-10S Perbandingan

Perbandingan bersamaan detil EPM3512AQI20810 dari Intel dan EPM3512AQC208-10S dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.

Perbandingan Spesifikasi

Parameter Umum EPM3512AQI20810 EPM3512AQC208-10S
Merek Intel Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup NRND Obsolete
Family MAX 3000A MAX 3000A
Macrocells 512 512
Usable Gates 10,000 1750
Logic Array Blocks (LABs) 16 (32 macrocells each) 32 (16 macrocells each)
Maximum User I/O Pins 172 —
Pin-to-Pin Propagation Delay (tPD) 10 ns —
Internal fMAX (logic feedback) 87 MHz —
Supply Voltage (VCCINT) 3.0 V to 3.6 V —
MultiVolt I/O Interface 1.8 V / 2.5 V / 3.3 V / 5.0 V compatible —
Paket 208-pin PQFP (PQ208) 208-pin FineLine BGA-256
Tipe Mounting Surface Mount —
Process Technology 0.30 µm CMOS EEPROM EEPROM-based CMOS
In-System Programmability IEEE Std. 1149.1 JTAG + IEEE Std. 1532 —
Suhu Kerja -40 °C to +85 °C (Industrial, "I" suffix) 0C to +70C (commercial)
Lead-Free / RoHS Contains lead / RoHS non-compliant (per Altera datasheet marking) —
Device Type — CPLD (Complex Programmable Logic Device)
User I/Os — 208
Speed Grade — -10 (tPD1 = 7.5 ns)
Propagation Delay (tPD1) — 7.5 ns (pin-to-pin)
Supply Voltage - VCCINT (internal) — 3.3 V
Supply Voltage - VCCIO (I/O) — 2.5 V, 3.3 V, or 5.0 V (MultiVolt)
Programming Technology — CMOS EEPROM
In-System Programmability (ISP) — Yes (IEEE Std. 1149.1 JTAG)
PCI Compliance — Yes (PCI Local Bus Specification Rev 2.2)
Boundary-Scan (JTAG) — Yes (1149.1 compliant)
Program/Erase Endurance — 100 cycles minimum
Logic Family — CMOS
Status RoHS — [DATA_NEEDED: rohs_status]

Spek dan Sumber

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