EPM5032JC vs EPM5032DI25 Perbandingan
Perbandingan bersamaan detil EPM5032JC dari Altera dan EPM5032DI25 dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.
Perbandingan Spesifikasi
| Parameter Umum | EPM5032JC | EPM5032DI25 |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Obsolete |
| Family | MAX 5000 EPLD | MAX 5000 |
| Macrocells | 32 | 32 |
| Logic Gates | 600 usable gates | — |
| Maximum I/O Pins | 40 | — |
| Propagation Delay (tPD) | [DATA_NEEDED: specific speed grade value] | — |
| Supply Voltage (VCC) | 5 V | 5 V (single supply) |
| Input Type | TTL-compatible | — |
| Tipe Output | TTL/CMOS-compatible | — |
| Paket | PLCC-44 | 24-pin Ceramic DIP (DI) with quartz window |
| Suhu Kerja | 0C to +70C (commercial) | — |
| Tipe Mounting | Surface Mount (J-lead) | — |
| Programmability | UV-erasable (windowed ceramic) / OTP variants | — |
| Design Software | MAX+PLUS II / Quartus legacy | — |
| JEDEC Standard | JEDEC PLCC-44 footprint | — |
| Status RoHS | unknown | — |
| Lead-Free | unknown | — |
| Device Type | — | UV-erasable EPLD (CMOS EPROM-based) |
| Logic Array Blocks (LABs) | — | 2 |
| Product Terms | — | 320 |
| Output Macrocells | — | 16 |
| Bidirectional I/O Pins | — | 16 |
| Dedicated Inputs | — | 7 |
| Total Inputs | — | 24 |
| Pin-to-Pin Delay (tPD) | — | 25 ns |
| Maximum Clock Frequency (fMAX) | — | 62.5 MHz |
| I/O Standard | — | TTL-compatible |
| Programming Technology | — | UV-EPROM (erasable via quartz window) |