EPM5064JC vs EPM5064JC1 Perbandingan
Perbandingan bersamaan detil EPM5064JC dari Altera dan EPM5064JC1 dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.
Perbandingan Spesifikasi
| Parameter Umum | EPM5064JC | EPM5064JC1 |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Obsolete |
| Family | MAX 5000 | MAX 5000 |
| Device Type | EPLD (Erasable PLD) | CPLD / EPLD (Erasable PLD) |
| Macrocells | 64 | 64 |
| Usable Gates | 1,250 (approx.) | 1.25K |
| Logic Array Inputs | 36 | — |
| Logic Array Outputs | 64 | — |
| Paket | 68-pin PLCC (JEDEC) | 44-pin PLCC (J-Lead) |
| Tipe Mounting | Surface Mount (socketed) | — |
| Supply Voltage (VCC) | 5 V (typical, 4.75 V - 5.25 V range) | — |
| I/O Logic Level | TTL / CMOS compatible | — |
| Configuration Memory | EPROM (UV-erasable window or OTP) | — |
| Suhu Kerja | [DATA_NEEDED: operating temperature grade] | — |
| Pin-to-Pin Delay (tPD) | [DATA_NEEDED: specific tPD grade value] | — |
| Maximum Frequency (fMAX) | [DATA_NEEDED: fCNT grade value] | — |
| Status RoHS | [DATA_NEEDED: RoHS compliance] | unknown |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Level MSL | [DATA_NEEDED: MSL rating] | — |
| Programming Tool | Altera MAX+PLUS II / Quartus II (legacy device support) | — |
| Logic Array Blocks (LABs) | — | 4 |
| Maximum Operating Frequency (fCNT) | — | 62.5 MHz |
| External Clock Input (max) | — | 50 MHz |
| I/O Pins | — | 28 |
| Dedicated Inputs | — | 7 |
| Total Inputs | — | 36 (28 I/O + 7 dedicated + 1 clock) |
| Operating Voltage (VCC) | — | 5 V |
| Program Type | — | EPROM (one-time programmable, UV-erasable) |
| Process Technology | — | CMOS |
| Operating Temperature (JC suffix) | — | 0°C to +70°C (commercial) |
| Supply Current (ICC) | — | [DATA_NEEDED: ICC maximum] |
| Lead-Free Status | — | unknown |