EPM570T100A5N vs EPM570GT100I5 Perbandingan

Perbandingan bersamaan detil EPM570T100A5N dari Altera dan EPM570GT100I5 dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.

Perbandingan Spesifikasi

Parameter Umum EPM570T100A5N EPM570GT100I5
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Aktif Aktif
Device Family MAX II —
Logic Elements 570 —
Macrocells 440 440
User I/O Pins 76 —
Number of Logic Array Blocks (LABs) 57 —
Paket 100-pin TQFP 100-pin TQFP (14x14 mm, 0.5 mm pitch)
Pin-to-Pin Logic Delay (tPD) 5.4 ns —
Maximum Internal Frequency 304 MHz —
Core Supply Voltage (VCCINT) 1.8 V (typical) —
I/O Supply Voltage (VCCIO) 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt) —
User Flash Memory (UFM) 8 Kbits —
Configuration Memory On-chip non-volatile flash —
Programming Interface JTAG (IEEE 1149.1) - ISP —
Suhu Kerja -40 °C to +125 °C (industrial) -40 C to +100 C (Industrial, "I5")
Tipe Mounting Surface Mount Surface Mount (Gull-wing leads)
Status RoHS Compliant Compliant
Series — MAX II
Logic Elements (LE) — 570
Maximum User I/O Pins — 76
Propagation Delay (tPD) — 5.4 ns (typ)
Internal Supply Voltage (VCCINT) — 1.71 V to 1.89 V
User I/O Voltage (VCCIO) — 1.5 V / 1.8 V / 2.5 V / 3.3 V (MultiVolt)
User Flash Memory — 8 Kbits
Programmability — In-System Programmable (ISP) via JTAG, non-volatile flash
Configuration Time — Instant-On (< 1 ms, no external PROM required)
Typical Active Current — [DATA_NEEDED: typical active ICC]
Speed Grade — GT (fast)
JTAG Support — IEEE 1149.1 boundary scan
Global Clock Networks — 4

Spek dan Sumber

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