EPM7128STI100-10N vs EPM7128ATC100-10 Perbandingan
Perbandingan bersamaan detil EPM7128STI100-10N dari Altera dan EPM7128ATC100-10 dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.
Altera
EPM7128STI100-10N - 128-Macrocell CPLD, 10ns, 100-pin TQFP | Altera
EPM7128STI100-10N ObsoleteAltera
EPM7128ATC100-10 - MAX 7000A CPLD, 128 Macrocells, 10ns TQFP-100 | Altera
EPM7128ATC100-10 ObsoletePerbandingan Spesifikasi
| Parameter Umum | EPM7128STI100-10N | EPM7128ATC100-10 |
|---|---|---|
| Merek | Altera | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | Obsolete | Obsolete |
| Family | MAX 7000S | MAX 7000A |
| Architecture | CMOS EEPROM-based CPLD | Multiple Array MatriX (MAX) |
| Macrocells | 128 | 128 |
| Usable Gates | 2,500 (up to 5,000 family max) | 2.5K |
| Logic Array Blocks (LABs) | 8 | 4 |
| Maximum User I/O | 84 | — |
| Pin-to-Pin Logic Delay (tPD) | 10 ns | — |
| Maximum Counter Frequency | 175.4 MHz | — |
| Supply Voltage (VCC) | 5 V | — |
| In-System Programmability | Yes (JTAG IEEE 1149.1) | Yes (IEEE 1149.1 JTAG) |
| JTAG Boundary-Scan | Yes (BST) | — |
| Paket | 100-pin TQFP | 100-pin TQFP (TC100) |
| Suhu Kerja | -40C to +85C (Industrial) | 0C to +70C (commercial) |
| Tipe Mounting | Surface Mount | Surface Mount |
| Level MSL | [DATA_NEEDED: MSL level] | — |
| Status RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance] |
| Open-Drain I/O Option | Available (per MAX 7000A feature set) | — |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| User I/O Pins | — | 68 |
| Pin-to-Pin Logic Delay | — | 4.5 ns |
| Counter Frequency (max) | — | 227.3 MHz |
| Speed Grade | — | -10 (10 ns) |
| Core Supply Voltage | — | 3.3 V |
| I/O Logic Level Support | — | 5.0 V / 3.3 V / 2.5 V (MultiVolt) |
| Program Memory | — | EEPROM (non-volatile) |