EPM7128STI100-10N vs EPM7128ATC100-10 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM7128STI100-10N sa pamamagitan ng Altera at EPM7128ATC100-10 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Pagsanggunian na paghahambing

Parametro EPM7128STI100-10N EPM7128ATC100-10
Brand Altera Altera
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Obsolete Obsolete
Family MAX 7000S MAX 7000A
Architecture CMOS EEPROM-based CPLD Multiple Array MatriX (MAX)
Macrocells 128 128
Usable Gates 2,500 (up to 5,000 family max) 2.5K
Logic Array Blocks (LABs) 8 4
Maximum User I/O 84 —
Pin-to-Pin Logic Delay (tPD) 10 ns —
Maximum Counter Frequency 175.4 MHz —
Supply Voltage (VCC) 5 V —
In-System Programmability Yes (JTAG IEEE 1149.1) Yes (IEEE 1149.1 JTAG)
JTAG Boundary-Scan Yes (BST) —
Packhaging 100-pin TQFP 100-pin TQFP (TC100)
Temperature na Operasyon -40C to +85C (Industrial) 0C to +70C (commercial)
Uri ng Pagpapasok Surface Mount Surface Mount
Level ng MSL [DATA_NEEDED: MSL level] —
Tindminan RoHS [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS compliance]
Open-Drain I/O Option Available (per MAX 7000A feature set) —
Product Type — CPLD (Complex Programmable Logic Device)
User I/O Pins — 68
Pin-to-Pin Logic Delay — 4.5 ns
Counter Frequency (max) — 227.3 MHz
Speed Grade — -10 (10 ns)
Core Supply Voltage — 3.3 V
I/O Logic Level Support — 5.0 V / 3.3 V / 2.5 V (MultiVolt)
Program Memory — EEPROM (non-volatile)

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