EPM9320GC280-15 vs EPM9320GC280-20 Perbandingan

Perbandingan bersamaan detil EPM9320GC280-15 dari Altera dan EPM9320GC280-20 dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.

Perbandingan Spesifikasi

Parameter Umum EPM9320GC280-15 EPM9320GC280-20
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete Obsolete
Family MAX 9000 (EPM9320) MAX 9000
Device Type CPLD - Complex Programmable Logic Device CPLD (Complex Programmable Logic Device)
Architecture CMOS EEPROM-based, Multiple Array MatriX (MAX) —
Usable Gates 6,000 6000 (approx.)
Macrocells 320 320
Logic Array Blocks (LABs) 20 (16 macrocells per LAB) 20 (16 macrocells each, typical for MAX 9000)
Pin-to-Pin Propagation Delay 15 ns —
Maximum Internal Frequency 117.6 MHz —
Maximum User I/O Pins 164 —
Supply Voltage (VCC) 4.75 V to 5.25 V 4.75 V to 5.25 V (5 V nominal)
I/O Voltage Levels 3.3 V or 5 V (configurable) —
Programmability 5.0-V in-system programmable (ISP) via IEEE 1149.1 JTAG —
Paket 280-pin Ceramic Pin Grid Array (CPGA-280) 280-pin Ceramic Pin Grid Array (CPGA)
Tipe Mounting Through-hole (PGA socket) Through-Hole (PGA socket)
Suhu Kerja 0 C to +70 C (commercial) [DATA_NEEDED: operating temperature grade]
Level MSL 3 (168 hours) —
Status RoHS ROHS3 compliant (per fpgalink listing) unknown
Technology Node CMOS EEPROM, third-generation MAX —
Maximum Operating Frequency — 100 MHz (internal counter)
Propagation Delay (tpd) — 23 ns (approx., -20 speed grade)
Technology — CMOS EEPROM
In-System Programmability — Yes (5.0-V ISP via JTAG)
JTAG Support — IEEE Std. 1149.1 compliant
Configuration Memory — EEPROM (non-volatile, instant-on)

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