EPM9320LC84-10 vs EPM9400LC84-15 Perbandingan
Perbandingan bersamaan detil EPM9320LC84-10 dari Intel dan EPM9400LC84-15 dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.
Perbandingan Spesifikasi
| Parameter Umum | EPM9320LC84-10 | EPM9400LC84-15 |
|---|---|---|
| Merek | Intel | Altera |
| Kategori | FPGA & CPLD | FPGA & CPLD |
| Status Lingkungan Hidup | NRND | Obsolete |
| Family | MAX 9000 EPLD | MAX 9000 |
| Device | EPM9320 | — |
| Macrocells | 320 | — |
| Usable Gates | 6000 (typical) | 8,000 |
| Logic Array Blocks (LABs) | 16 | — |
| Maximum User I/O Pins | 168 (varies by package) | — |
| Pin-to-Pin Logic Delay (tPD) | 10 ns | — |
| Maximum Frequency (fCNT) | [DATA_NEEDED: fCNT in MHz] | — |
| Supply Voltage (VCC) | 5.0 V (typical, see datasheet) | — |
| Process Technology | 0.7 µm CMOS EEPROM/UV-EPROM | — |
| Paket | 84-pin PLCC (JEDEC MO-047) | 84-pin PLCC |
| Tipe Mounting | Surface Mount (PLCC socket also common) | Surface Mount |
| Suhu Kerja | 0C to +70C (commercial) [DATA_NEEDED: exact grade suffix] | 0C to +70C (Commercial) |
| Programming Interface | JTAG (IEEE 1149.1) boundary-scan, Altera ByteBlaster compatible | — |
| Configuration | Non-volatile EEPROM (instant-on, no boot PROM) | — |
| Status RoHS | ROHS3 Compliant (per fpgalink listing) | [DATA_NEEDED: RoHS status] |
| Tingkat Sensitivitas Kekeringan (MSL) | MSL-3, 168 hours (per fpgalink listing) | — |
| Manufacturer Lead Time | 1-7 days (per fpgalink listing) | — |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Macro Cells | — | 400 |
| Logic Array Blocks | — | 25 |
| Maximum User I/Os | — | 59 |
| Maximum Operating Frequency | — | 117.6 MHz |
| Speed Grade | — | -15 (15 ns pin-to-pin delay) |
| Core Supply Voltage (VCCINT) | — | 5.0 V |
| Input Logic Compatibility | — | TTL, 3.3 V and 5.0 V tolerant |
| Configuration Memory | — | EEPROM (non-volatile, in-system programmable) |
| JTAG Interface | — | IEEE Std. 1149.1 compliant (ISP) |
| Minimum VCCINT | — | 4.75 V |
| Programming Method | — | In-System Programmable via JTAG |