EPM9320LC84-10 vs EPM9400LC84-15 Comparison
Detailed side-by-side comparison of EPM9320LC84-10 by Intel and EPM9400LC84-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9320LC84-10 | EPM9400LC84-15 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $84.96 | $23.10 |
| Family | MAX 9000 EPLD | MAX 9000 |
| Device | EPM9320 | β |
| Macrocells | 320 | β |
| Usable Gates | 6000 (typical) | 8,000 |
| Logic Array Blocks (LABs) | 16 | β |
| Maximum User I/O Pins | 168 (varies by package) | β |
| Pin-to-Pin Logic Delay (tPD) | 10 ns | β |
| Maximum Frequency (fCNT) | [DATA_NEEDED: fCNT in MHz] | β |
| Supply Voltage (VCC) | 5.0 V (typical, see datasheet) | β |
| Process Technology | 0.7 Β΅m CMOS EEPROM/UV-EPROM | β |
| Package | 84-pin PLCC (JEDEC MO-047) | 84-pin PLCC |
| Mounting Type | Surface Mount (PLCC socket also common) | Surface Mount |
| Operating Temperature | 0C to +70C (commercial) [DATA_NEEDED: exact grade suffix] | 0C to +70C (Commercial) |
| Programming Interface | JTAG (IEEE 1149.1) boundary-scan, Altera ByteBlaster compatible | β |
| Configuration | Non-volatile EEPROM (instant-on, no boot PROM) | β |
| RoHS Status | ROHS3 Compliant (per fpgalink listing) | [DATA_NEEDED: RoHS status] |
| Moisture Sensitivity Level (MSL) | MSL-3, 168 hours (per fpgalink listing) | β |
| Manufacturer Lead Time | 1-7 days (per fpgalink listing) | β |
| Device Type | β | CPLD (Complex Programmable Logic Device) |
| Macro Cells | β | 400 |
| Logic Array Blocks | β | 25 |
| Maximum User I/Os | β | 59 |
| Maximum Operating Frequency | β | 117.6 MHz |
| Speed Grade | β | -15 (15 ns pin-to-pin delay) |
| Core Supply Voltage (VCCINT) | β | 5.0 V |
| Input Logic Compatibility | β | TTL, 3.3 V and 5.0 V tolerant |
| Configuration Memory | β | EEPROM (non-volatile, in-system programmable) |
| JTAG Interface | β | IEEE Std. 1149.1 compliant (ISP) |
| Minimum VCCINT | β | 4.75 V |
| Programming Method | β | In-System Programmable via JTAG |