EPM9560RC208-10 vs EPM9560RC208-15C Perbandingan

Perbandingan bersamaan detil EPM9560RC208-10 dari Intel dan EPM9560RC208-15C dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.

Perbandingan Spesifikasi

Parameter Umum EPM9560RC208-10 EPM9560RC208-15C
Merek Intel Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete Obsolete
Family MAX 9000 MAX 9000
Device Type CPLD (Complex Programmable Logic Device) EEPROM-based CPLD (EPLD)
Macrocells 560 560
Logic Array Blocks (LABs) 16 —
Maximum User I/O Pins 212 (208-pin package variant) —
Usable Gates 12,000 12,000
Pin-to-Pin Delay (tPD) 10 ns —
Maximum Frequency (fMAX) [DATA_NEEDED: internal toggle frequency in MHz] —
Supply Voltage (VCCINT) 5.0 V —
I/O Standards Supported 5.0 V TTL, 3.3 V LVTTL, 2.5 V (multiVolt I/O) —
Configuration Memory EEPROM (in-system programmable via JTAG) EEPROM (non-volatile)
Process Technology 0.30 µm CMOS EEPROM —
Suhu Kerja 0C to +70C (commercial) —
Paket 208-pin RQFP (Plastic Quad Flat Pack) 208-pin RQFP
Tipe Mounting Surface Mount Surface Mount
Lead-Free [DATA_NEEDED: confirm lead-free status -10 suffix is conventional Pb-containing] —
Status RoHS [DATA_NEEDED: not stated in retrieved distributor listings] [DATA_NEEDED: RoHS status]
Programmability JTAG (IEEE 1149.1) in-system programming —
User I/O Pins — 149
Propagation Delay (tPD) — 15 ns
Maximum Counter Frequency — 117.6 MHz
Supply Voltage Range — 4.75 V to 5.25 V
Nominal Supply Voltage — 5.0 V
I/O Voltage Compatibility — 3.3 V or 5 V
In-System Programmability — Yes, via IEEE Std. 1149.1 JTAG
Rentang Suhu Kerja — 0C to +70C (commercial)
Speed Grade — -15 (15 ns)
Logic Architecture — Multiple Array MatriX (MAX) third generation

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