EPM9560RC208-12 vs EPM9560RC208-10 Perbandingan

Perbandingan bersamaan detil EPM9560RC208-12 dari Altera dan EPM9560RC208-10 dari Intel. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.

Perbandingan Spesifikasi

Parameter Umum EPM9560RC208-12 EPM9560RC208-10
Merek Altera Intel
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete Obsolete
Family MAX 9000 MAX 9000
Device Type EEPROM-based CPLD CPLD (Complex Programmable Logic Device)
Macrocells 560 560
Flip-Flops 772 —
Usable Gates 12000 12,000
User I/O Lines 153 —
Propagation Delay (tPD) 12 ns —
Frekuensi Bawah Maximum 125 MHz —
Supply Voltage (VCCINT) 5 V 5.0 V
I/O Voltage Compatibility 3.3 V or 5 V —
Paket 208-pin RQFP (S-PQFP-G208) 208-pin RQFP (Plastic Quad Flat Pack)
Terminal Pitch 0.50 mm —
Suhu Kerja 0C to +70C (commercial) 0C to +70C (commercial)
Tipe Mounting Surface Mount Surface Mount
Configuration Memory EEPROM (non-volatile) EEPROM (in-system programmable via JTAG)
Logic Array Blocks 20 —
Speed Grade -12 (12 ns) —
Status RoHS [DATA_NEEDED: RoHS status] [DATA_NEEDED: not stated in retrieved distributor listings]
Logic Array Blocks (LABs) — 16
Maximum User I/O Pins — 212 (208-pin package variant)
Pin-to-Pin Delay (tPD) — 10 ns
Maximum Frequency (fMAX) — [DATA_NEEDED: internal toggle frequency in MHz]
I/O Standards Supported — 5.0 V TTL, 3.3 V LVTTL, 2.5 V (multiVolt I/O)
Process Technology — 0.30 µm CMOS EEPROM
Lead-Free — [DATA_NEEDED: confirm lead-free status -10 suffix is conventional Pb-containing]
Programmability — JTAG (IEEE 1149.1) in-system programming

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