EPM9560RC208-12 vs EPM9560RC208-10 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM9560RC208-12 sa pamamagitan ng Altera at EPM9560RC208-10 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM9560RC208-12 | EPM9560RC208-10 |
|---|---|---|
| Brand | Altera | Intel |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | MAX 9000 | MAX 9000 |
| Device Type | EEPROM-based CPLD | CPLD (Complex Programmable Logic Device) |
| Macrocells | 560 | 560 |
| Flip-Flops | 772 | — |
| Usable Gates | 12000 | 12,000 |
| User I/O Lines | 153 | — |
| Propagation Delay (tPD) | 12 ns | — |
| Maksimum na Taktiko ng Oras | 125 MHz | — |
| Supply Voltage (VCCINT) | 5 V | 5.0 V |
| I/O Voltage Compatibility | 3.3 V or 5 V | — |
| Packhaging | 208-pin RQFP (S-PQFP-G208) | 208-pin RQFP (Plastic Quad Flat Pack) |
| Terminal Pitch | 0.50 mm | — |
| Temperature na Operasyon | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Configuration Memory | EEPROM (non-volatile) | EEPROM (in-system programmable via JTAG) |
| Logic Array Blocks | 20 | — |
| Speed Grade | -12 (12 ns) | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: not stated in retrieved distributor listings] |
| Logic Array Blocks (LABs) | — | 16 |
| Maximum User I/O Pins | — | 212 (208-pin package variant) |
| Pin-to-Pin Delay (tPD) | — | 10 ns |
| Maximum Frequency (fMAX) | — | [DATA_NEEDED: internal toggle frequency in MHz] |
| I/O Standards Supported | — | 5.0 V TTL, 3.3 V LVTTL, 2.5 V (multiVolt I/O) |
| Process Technology | — | 0.30 µm CMOS EEPROM |
| Lead-Free | — | [DATA_NEEDED: confirm lead-free status -10 suffix is conventional Pb-containing] |
| Programmability | — | JTAG (IEEE 1149.1) in-system programming |