EPM9560RC208-20C vs EPM9560RC210-20 Perbandingan

Perbandingan bersamaan detil EPM9560RC208-20C dari Altera dan EPM9560RC210-20 dari Altera. Bandingkan spesifikasi penting, parameter listrik, pengemasan, status cycle, harga, dan ketersediaan untuk menentukan komponen terbaik untuk kebutuhan desain Anda.

Altera
EPM9560RC210-20 EPM9560RC210-20 - MAX 9000 CPLD 560 Macrocells | Altera

EPM9560RC210-20 - MAX 9000 CPLD 560 Macrocells | Altera

EPM9560RC210-20 ⚠ Waktu Beli Terakhir

Perbandingan Spesifikasi

Parameter Umum EPM9560RC208-20C EPM9560RC210-20
Merek Altera Altera
Kategori FPGA & CPLD FPGA & CPLD
Status Lingkungan Hidup Obsolete Waktu Pembelian Terakhir
Family MAX 9000 MAX 9000
Device Type EEPROM-based CPLD (EE PLD) —
Macrocells 560 560
Usable Gates 12,000 12,000
Flip-Flops 772 —
Configurable I/O Lines 149 —
Propagation Delay (tPD) 20 ns (speed grade -20) —
Maximum Frequency 100 MHz —
Tegangan Pemuat 5.0 V 5 V
I/O Voltage Support 3.3 V or 5 V —
Configuration Memory EEPROM (non-volatile) —
In-System Programmability Yes, via IEEE Std. 1149.1 JTAG Yes (MAX+PLUS II flow)
Paket 208-pin RQFP (Power Quad Flat Pack) RQFP-210 (Power Quad Flat Pack, 0.5mm pitch)
JESD-30 Package Code S-PQFP-G208 —
Terminal Form Gull Wing —
Operating Temperature Grade Commercial (0C to +70C) —
Technology CMOS —
Tipe Mounting Surface Mount Surface Mount
Status RoHS [DATA_NEEDED: RoHS status] RoHS3 Compliant (per supplier listing)
Product Type — CPLD (Complex Programmable Logic Device)
Logic Array Blocks (LABs) — 16
Pin-to-Pin Delay (tPD) — 20 ns
Clock-to-Output (tCO) — 12 ns
Maximum User I/O — [DATA_NEEDED: 212 I/O per datasheet, package-dependent]
Process Technology — 0.65 um EEPROM
Boundary-Scan (JTAG) — IEEE Std 1149.1 compliant
Suhu Kerja — [DATA_NEEDED: commercial 0C to 70C typical; industrial variants exist]

Spek dan Sumber

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