STM32F103RET6：エンジニア向け完全ガイド — 仕様、ピン配置、代替品、調達（2026年）

The STM32F103RET6 is a 32-bit ARM Cortex-M3 microcontroller from STMicroelectronics that runs at up to 72 MHz with 512 KB of Flash, 64 KB of SRAM, and 51 GPIO pins in a 64-pin LQFP (10x10 mm) package. It operates from a 2.0 V to 3.6 V supply across the industrial -40°C to +85°C range and integrates three 12-bit ADCs, four general-purpose 16-bit timers, two advanced PWM timers, five USARTs, three SPIs, two I2C buses, USB 2.0 full-speed device, CAN 2.0B, and SDIO. The part is in active production and currently available from XAIPART with 62,000 units in stock, MOQ 1, at $3.7969 for qty 1 down to $2.2148 per unit at 1,000 pieces as of 2026-10-18. This guide covers selection criteria, design-in practice, drop-in alternatives, and sourcing risk for engineers building motor drives, industrial gateways, medical meters, PLC I/O, USB HID devices, and HMI panels.

Why do engineers still choose the STM32F103RET6?

The STM32F103RET6 wins on the combination of memory density, peripheral mix, and second-source depth at a mainstream price point. The 512 KB Flash is organized in 128-bit wide banks for fast code execution and supports both in-system programming (ISP) via USART/USB and in-application programming (IAP) for field firmware upgrades — the combination that keeps the F1 line serviceable in deployed industrial equipment. The 64 KB SRAM accommodates TCP/IP stacks, USB HID stacks, and small RTOS kernels without an external memory chip.

The headline specs that drive selection:

Within ST's portfolio the F1 series sits between entry-level STM32F0 and mainstream STM32F4. The 72 MHz ceiling is the trade-off engineers accept to stay on the F1 line; if you need USB OTG or >100 MHz performance, that is a migration decision, not a variant decision. The optional memory protection unit (MPU) and 7-channel DMA controller offload data movement, and the 16-bit timers cascade into complex PWM and quadrature encoder chains for motor and power-conversion work.

Takeaway: choose the STM32F103RET6 when your firmware fits in 512 KB, you need CAN + USB + multiple USARTs without bridge chips, and you want a register-compatible second source — which exists, as shown below.

How do you design in the STM32F103RET6 correctly?

Three design areas determine whether an STM32F103RET6 board works on the first spin: power, boot configuration, and clock layout.

Power and analog supply. VDD accepts 2.0–3.6 V. VDDA (pin 9) feeds the ADC and reset blocks separately from digital VDD. Filter VDDA through a ferrite bead and decouple it locally with 100 nF plus 1 µF ceramic capacitors to keep ADC noise low, following the reference layouts in ST application note AN2586. With three 12-bit ADCs sampling up to 21 channels, analog supply quality directly determines effective resolution.

Boot mode. BOOT0 (pin 44) and BOOT1 (shared with PB2, pin 20) select the boot source at reset. Incorrect BOOT0 strapping is the most common bring-up failure: if BOOT0 floats or is pulled high unintentionally, the device boots to the system bootloader instead of Flash. Tie BOOT0 to ground through a resistor and expose it on a test point or jumper for ISP programming via USART or USB DFU.

Clock layout. The HSE crystal must be in the 4–16 MHz range; the LSE uses a 32.768 kHz crystal on PC14/PC15 (pins 3–4). Route both following ST AN2586 PCB guidelines to avoid RF interference, with short traces, ground guard, and local load capacitors.

Debug and programming. The JTAG/SWD pins are fixed functions: PA13 (JTMS-SWDIO, pin 34), PA14 (JTCK-SWCLK, pin 37), PA15 (JTDI, pin 38), PB3 (JTDO, pin 39), and PB4 (JTRST, pin 40). Even in SWD-only designs, break these pins out to a header; SWD plus the TRACEWO output on PB3 supports field diagnostics.

Peripheral pin planning. The LQFP-64 exposes 51 GPIO, and the remaining 13 pins are dedicated to VDD/VSS pairs, VDDA/VSSA, NRST, BOOT0, oscillator pins, and debug. Some functions remap, but the fixed functions constrain layout. Key shared pins to plan early: PA11/PA12 (USBDM/USBDP or CAN_RX/CAN_TX, pins 32–33) — you cannot use USB and CAN simultaneously on the default mapping; PB6/PB7 (I2C1, pins 42–43); PB10/PB11 (I2C2/USART3, pins 21–22).

Takeaway: strap BOOT0 to ground through a resistor, filter VDDA with a ferrite bead plus 100 nF/1 µF, and break out SWD and BOOT0 before routing — those three decisions prevent most first-spin failures.

Which applications does the STM32F103RET6 fit best?

The verified application set spans six scenarios, each anchored to specific peripherals:

• Three-phase BLDC/PMSM motor drives. The two advanced 16-bit timers generate complementary PWM with programmable dead-time; the 72 MHz core executes field-oriented control in well under 10 µs; the three 12-bit ADCs sample phase currents simultaneously at 1 µs conversion; CAN 2.0B streams telemetry. A 1 kW inverter running FOC at 20 kHz PWM leaves CPU margin for a small RTOS handling faults and encoder feedback.
• Industrial CAN-to-USB/Ethernet gateways. bxCAN 2.0B, USB 2.0 FS device, and five USARTs eliminate bridge chips. The Cortex-M3 NVIC services time-critical CAN RX interrupts deterministically within 12 cycles; 64 KB SRAM buffers frames at 1 Mbit/s bus loads; 512 KB Flash holds a CANopen or J1939 stack alongside gateway logic.
• Medical blood-glucose meters. The 12-bit ADC reads picoampere-scale currents through on-chip amplifiers; low-power Run/Sleep/Stop modes (down to ~10 µA in Standby) extend multi-month battery shelf life; USB 2.0 FS handles charging and log upload.
• PLC digital I/O modules. 51 GPIO drive opto-isolated inputs and relay coils; 7 DMA channels debounce and count pulses without CPU load; the industrial temperature range matches cabinet specifications.
• USB HID peripherals. The on-chip USB FS controller needs no external PHY; ST's USB Device Library provides ready HID, CDC, and DFU classes for fast bring-up.
• Consumer HMI touch panels. Three SPIs drive LCD controllers at 36 MHz; the ADC reads resistive touch; SDIO streams images from microSD; 64 KB SRAM holds double-buffered 320×240 RGB framebuffers.

Takeaway: if your product needs simultaneous motor control, CAN, and USB, the STM32F103RET6 covers it on one die; verify USB-vs-CAN pin sharing on PA11/PA12 before committing to the schematic.

What are the drop-in alternatives to the STM32F103RET6?

Three register-compatible second sources are verified in the XAIPART database. All three share the LQFP-64 footprint, 512 KB Flash, 64 KB SRAM, and the STM32F1 peripheral register map, so migration is a re-validation exercise rather than a redesign:

GD32F103RET6 is the most widely documented replacement. It runs at 108 MHz versus 72 MHz — a 50% clock advantage — but firmware timing assumptions must be re-checked, particularly delays derived from SysTick. It also carries roughly 30% lower unit cost, per the XAIPART sourcing data, making it the standard hedge against STM32 re-pricing.

APM32F103RET6 (Geehy) matches the STM32 clock-for-clock at 72 MHz, which makes it the lowest-risk swap when firmware timing is already validated and you want zero clock-dependent rework.

HK32F103RET6 (HKMicro) offers the same core, memory, footprint, and register-level compatibility with the STM32F1 standard library, providing a third sourcing lane.

Note one functional boundary: the STM32F103 line only offers USB full-speed device (no OTG), and GD32 mirrors that limitation, so there is no functional loss migrating between them — but neither upgrades you to OTG.

Takeaway: dual-source with GD32F103RET6 for cost and speed headroom, or APM32F103RET6 for a timing-identical swap; qualify the second source on your actual firmware, not just the schematic.

What does the STM32F103RET6 market and supply situation look like?

The STM32F103RET6 carries an active lifecycle status in the XAIPART product database. XAIPART currently lists 62,000 units in stock with MOQ 1 and tiered pricing at $3.7969 (qty 1), $2.7422 (qty 10), $2.4258 (qty 100), $2.3203 (qty 500), and $2.2148 (qty 1,000) as of 2026-10-18.

On third-party availability, the XAIPART FAQ data (as of 2026-10-10) reports the part in stock at DigiKey (1,852,094 units), Mouser, and the ST eStore, with qty-1 pricing around USD 8.20 and volume pricing near USD 4.85 at 1k pieces. Note the explicit conflict with the XAIPART direct pricing above ($3.7969 at qty 1 as of 2026-10-18): the two datasets were captured on different dates from different channels, so buyers should compare live quotes at order time rather than assume either figure. The same FAQ data records that during the 2020–2022 shortage, unit prices spiked above USD 25 — a 10× move that justified carrying a qualified second source. Lead-time data from the same source: DigiKey and Mouser shipped qty-1 to qty-1000 orders from stock with no factory lead time, 10k+ reels fulfilled in 6–10 weeks, and the ST eStore offered factory-direct stock with 3–5 day shipping to EU/US distributors.

Takeaway: with 62,000 units on the XAIPART shelf and three qualified register-compatible alternates, the supply risk on this part is second-source manageable, not allocation-driven — but keep a GD32F103RET6 design note in your BOM file in case pricing moves again.

What should buyers watch in 2026 and beyond?

First, the STM32F103RET6 remains suitable for new industrial and consumer designs in 2026: the F1 series is in active production, firmware libraries (HAL, SPL, LL) are stable, and second sources from GD32, APM32, and HK32 keep procurement flexible. The one hard boundary: the F1 lacks AEC-Q100 qualification, so engineers targeting long-lifecycle automotive should plan migration to STM32G0/G4 instead.

Second, watch the density family. The STM32F103RBT6 (128 KB Flash), SR, ZR, and CR variants share identical peripherals, RAM, and pinout in the same LQFP-64 footprint per the ST datasheet, so you can step density up or down without a layout change — useful when a product line branches into a low-cost SKU.

Third, if you adopt the GD32F103RET6 second source, audit SysTick-derived delays and any cycle-counted code against the 108 MHz versus 72 MHz clock difference. Everything that runs off peripheral registers behaves identically; software timing assumptions are the migration risk.

Fourth, monitor price spread between channels. The gap between the $2.2148 1k-piece XAIPART tier and the higher third-party qty-1 quotes in the FAQ data means volume buyers should negotiate at the 500–1000 tier, where the $2.3203 to $2.2148 step flattens.

Takeaway: design in the STM32F103RET6 with confidence for industrial 2026 launches, qualify one alternate, avoid it for AEC-Q100-qualified automotive programs, and buy at the 1k tier for best unit cost as of 2026-10-18.

For full pin definitions, ordering codes, and package drawings, download the official datasheet or visit the STM32F103RET6 product page on XAIPART. Browse the broader microcontroller lineup in the XAIPART component catalog, or read related sourcing analysis on the XAIPART blog.