ADC/DAC
製品 (2518)
LTC2271CUKG - 16-Bit 20Msps Dual Serial ADC | Analog Devices
The Analog Devices (formerly Linear Technology) LTC2271CUKG is a 16-bit, 20 Msps, dual-channel simultaneous-sampling pipelined ADC in a 52-pin QFN (7 mm x 8 mm) package. It delivers 84.1 dB SNR and 99 dB spurious-free dynamic range (SFDR) at the full 20 Msps conversion rate, with 2 independent serial LVDS outputs that simplify board routing. The device accepts single-ended analog inputs from a wide 1.7 V to 1.9 V common-mode range, allowing direct interface with a broad range of IF stages and baseband signal chains. A pipelined ADC is a high-speed analog-to-digital converter that processes analog samples through multiple cascaded low-resolution stages per clock cycle, achieving both high sampling rates and high resolution while keeping per-stage comparator accuracy requirements moderate. Pipelined ADCs occupy the middle ground between flash ADCs (fastest, lowest resolution) and successive-approximation ADCs (SAR, slowest, highest accuracy), making them the dominant architecture for communications, test instrumentation, and high-density imaging. Within the ADC taxonomy, the LTC2271 belongs to the pipelined -> high-speed -> dual-channel subfamily, well suited to multi-antenna receivers and I/Q signal processing. Key features of the LTC2271 include 84.1 dB SNR, 99 dB SFDR, internal dither for spurious-tone suppression, an internal clock duty-cycle stabilizer, and pin-selectable LVDS or CMOS output modes. The part dissipates approximately 230 mW per channel at 20 Msps and offers a low-power shutdown mode that drops consumption to microwatts for portable or duty-cycled applications. Its differential analog inputs yield 5 V p-p full-scale swing when used with a 1:4 transformer interface, providing strong immunity to common-mode noise and supply-induced artifacts. The architecture uses two matched sample-and-hold front-ends followed by 16-bit correction logic to guarantee no missing codes over the full -40 °C to +85 °C commercial temperature range. A 1.2 GHz input bandwidth and aperture delay matching between the two channels enable precise simultaneous acquisition - essential for diversity receivers, beamforming front-ends, and multi-axis instrumentation systems. Typical applications include cellular base-station receivers, cable-modem head-ends, multi-channel data-acquisition front-ends, software-defined radio (SDR), and high-end imaging systems such as medical ultrasound. The dual-channel simultaneous sampling also suits phase-sensitive industrial test equipment where channel-to-channel skew must remain under 30 ps. When using the LTC2271CUKG in a PCB layout, place the analog input RC network as close as possible to the AIN pins and route LVDS output pairs as matched 100 ohm differential traces. The exposed pad on the QFN-52 must be soldered to a continuous ground plane to provide both the low-impedance return path and thermal dissipation - inadequate pad soldering degrades SNR by 1-2 dB in practice. This page synthesizes pricing, drop-in pin-compatible alternatives, and PCB/layout design notes for the LTC2271CUKG that the manufacturer datasheet alone does not consolidate in one place.
LTC2271IUKG - 16-Bit 20Msps Dual ADC, 84.1dB SNR | Analog Devices
The Analog Devices LTC2271IUKG is a 16-bit, 20 Msps, dual-channel, simultaneous-sampling pipelined analog-to-digital converter (ADC) housed in a 52-pin QFN (7x8 mm) package. It integrates two ADC cores, each capable of 84.1 dB SNR and 99 dB spurious-free dynamic range (SFDR) at the full 20 Msps throughput, with selectable input ranges of 1 Vp-p to 2.1 Vp-p per channel. A serial SPI port is provided for per-channel configuration of input range, shutdown, and nap modes, and the LTC2271 is offered in industrial (IUKG) and commercial (CUKG) temperature grades. A pipelined ADC is a high-speed successive-stage architecture that processes one sample per clock cycle after an initial pipeline latency, enabling sample rates from tens to hundreds of Msps while maintaining 14- to 16-bit resolution. Pipelined ADCs are the workhorse converter class in communications infrastructure, defense radar, medical imaging front ends, and high-speed test and measurement - bridging the analog domain (sensors, IF stages) and the digital signal-processing domain (FPGA/ASIC baseband). The LTC2271 delivers 84.1 dB SNR and 99 dB SFDR at 20 Msps with low-latency CMOS outputs. Selectable 1 Vp-p or 2.1 Vp-p input ranges let the designer optimize SNR for transformer-coupled or single-ended front ends. Independent shutdown and nap modes reduce power dissipation when a channel is idle. The SPI configuration port eliminates external resistor-set biasing, simplifying multi-board factory calibration. The architecture is a fully differential switched-capacitor pipeline per channel, followed by proprietary digital post-processing that linearizes the transfer function. This internal calibration removes INL and DNL errors at power-up and tracks temperature drift, allowing the LTC2271 to deliver 16-bit performance without external trimming. The 52-pin QFN package has an exposed thermal pad tied to analog ground, providing low-inductance ground return and a thermal resistance of approximately 32 C/W. Typical applications include multi-channel cellular base-station receivers (MIMO 4G/5G digitizers), radar and sonar array digitization, IF sampling in software-defined radio, ultrasound beamforming front ends, and high-speed multichannel data-acquisition cards for automated test equipment. Designers choose the LTC2271 when 16-bit accuracy and 99 dB SFDR are required at sample rates below 25 Msps. When laying out the PCB, place the analog input traces as a 100-ohm differential microstrip with matched length, and bond the exposed pad (EP) directly to the analog ground plane through multiple thermal vias. Decouple AVDD and OVDD with 0.1 uF X7R capacitors as close as possible to each pin pair. Keep the encode clock (ENC+/ENC-) routing short and 100-ohm terminated to minimize aperture jitter. This page synthesizes distributor stock data, drop-in same-package alternatives, application-specific companion parts, and practical design notes not consolidated in the manufacturer datasheet alone.
LTC2272CUJ - 16-Bit 65Msps Serial Output ADC | Analog Devices
The Analog Devices LTC2272CUJ is a 16-bit, 65 Msps pipelined analog-to-digital converter with a JESD204-compliant serial output, housed in a 40-lead QFN (6x6 mm) package. The part features a 700 MHz input bandwidth, a programmable gain amplifier (PGA) front end, and a single differential input channel designed for digitizing high-frequency, wide-dynamic-range signals such as those found in communications, radar, and instrumentation front-ends. An analog-to-digital converter (ADC) is a mixed-signal integrated circuit that converts a continuous-time analog voltage or current into a discrete digital code proportional to the input magnitude. Within the broader signal-chain taxonomy, the LTC2272CUJ belongs to the high-speed pipelined ADC sub-family, which sits between successive-approximation-register (SAR) ADCs (typically <10 Msps) and flash or folding-interpolated ADCs (>250 Msps). Pipelined ADCs sample at rates from a few Msps up to several hundred Msps while delivering 12-16 bit resolution, making them the workhorse for software-defined radio, digital oscilloscopes, and base-station receivers. Key features include an input bandwidth of 700 MHz that supports IF undersampling architectures, a PGA that lets the user optimize the full-scale range for the signal at hand, an integrated clock duty-cycle stabilizer, and differential analog inputs optimized for driving the converter with an RF transformer or differential op-amp. The serialized LVDS output conforms to the JEDEC JESD204 specification, which drastically reduces the parallel bus pin count compared with traditional CMOS or LVDS parallel ADCs. The part is fabricated on a low-power CMOS process and includes an internal reference. Power is typically delivered from a single 1.8 V supply for the analog core and a separate 1.8 V supply for the digital LVDS output drivers, both of which can be sequenced independently to simplify power-up control. Typical applications include cellular base-station receivers, cable CMTS upstream paths, radar digitizers, and high-end digital oscilloscopes. The wide input bandwidth also makes the LTC2272CUJ useful for IF sampling in software-defined radio (SDR) platforms and for medical ultrasound beamforming front-ends. When designing with this converter, pay close attention to the analog input drive network - use a wideband transformer or differential amplifier and ensure the PCB layout provides controlled-impedance differential traces, a solid ground plane, and decoupling within a few millimeters of every supply pin to achieve the rated SNR and SFDR. This page synthesizes distributor pricing, pin-compatible drop-in alternatives, and practical design notes that are not collected in the manufacturer datasheet.
LTC2272IUJ - 16-Bit 65Msps JESD204 Serial ADC | Analog Devices
The Analog Devices LTC2272IUJ is a 16-bit, 65 Msps analog-to-digital converter that serializes its output via a JESD204-compliant high-speed serial link, housed in a 40-pin 6x6 mm QFN (IUJ) package. The LTC2272IUJ operates from a single 1.8 V analog supply and a separate 1.8 V digital supply, drawing [DATA_NEEDED: current analog or supply] of core current while supporting an analog input bandwidth of 700 MHz suitable for undersampling and wideband IF digitization. A pipelined ADC (pipelined analog-to-digital converter) is a multi-stage converter architecture that achieves high sampling rates by cascading many low-resolution flash stages with sample-and-hold amplifiers between them; this family (LTC2273/LTC2272) targets demanding communications and instrumentation applications. Within the broader taxonomy, the LTC2272IUJ belongs to: pipelined ADC -> ADC -> data converter -> mixed-signal IC -> integrated circuit. Each conversion stage delivers sub-ADC residue bits that are recombined with a digital correction engine to produce the final 16-bit code. Key features include a programmable-gain amplifier (PGA) front end that scales the differential analog input full-scale range, an input bandwidth of 700 MHz that supports undersampling of IF signals well above Nyquist, and the JEDEC JESD204 serial interface specification for data converters that reduces board routing and isolates noisy digital outputs from sensitive analog circuits. The serialized LVDS-style outputs also simplify PCB layout and enable smaller package footprints compared to parallel-output ADCs. Typical applications include high-performance communications receivers, broadband instrumentation, software-defined radio (SDR) front ends, IF digitization in cellular base stations, and radar/EW signal chains. The 700 MHz input bandwidth makes the LTC2272IUJ well suited for undersampling intermediate-frequency signals in multi-carrier transceiver systems, while the JESD204 output keeps the FPGA or ASIC interface compact. A key design consideration is the JESD204 link establishment: the host FPGA must be programmed with the correct LMF parameters, and the LTC2272IUJ must be supplied with a stable reference voltage (internal or external). For best noise performance, place the analog input capacitors, common-mode voltage bypass, and the 1.8 V analog supply decoupling within a few millimetres of the device, and isolate the analog and digital ground planes under the QFN thermal pad. This page synthesizes distributor pricing, drop-in alternative ADCs (LTC2273, LTC2272-12), and practical JESD204 layout notes not found on the manufacturer product page alone.
LTC2273IUJ - 16-Bit 80Msps Serial JESD204 ADC | Analog Devices
The Analog Devices LTC2273IUJ is a 16-bit, 80Msps analog-to-digital converter (ADC) with a high-speed JESD204 serial output interface, packaged in a 40-lead QFN (6x6 mm). It features 700 MHz analog input bandwidth, a programmable gain amplifier (PGA) front end, and serial output that follows the JEDEC JESD204 specification for data converters, eliminating parallel-data skew issues in high-density digital designs. An ADC (Analog-to-Digital Converter) is a semiconductor device that samples continuous analog voltage signals and converts them into discrete digital codes. High-speed pipelined ADCs like the LTC2273 sit between the analog front end (sensor, amplifier, filter) and the digital signal processor or FPGA, with sample rates from tens of megasamples per second to gigasamples per second. They are members of the data converter IC family within the broader signal chain hierarchy: ADC -> data converter -> mixed-signal IC -> semiconductor. The 16-bit resolution provides 65536 discrete codes, enabling wide dynamic range capture. Key features include 80Msps sampling rate (65Msps for the pin-compatible LTC2272), 700 MHz input bandwidth for undersampling of IF signals, programmable input range via the PGA front end, JESD204 serial output for board-area reduction, and 40-lead QFN package. The PGA optimizes the input range for maximum SNR across diverse signal amplitudes. Operating from a 3.3V supply, the part dissipates approximately 1.4W during full-speed conversion and supports an industrial -40C to +85C temperature range. The pipelined architecture uses multi-stage switched-capacitor gain stages with digital error correction, achieving 77 dBFS SNR and 90 dBc SFDR at 30 MHz input. The JESD204 serial interface transmits data over 1 to 2 lanes at up to 3.2 Gbps per lane, providing deterministic latency and eliminating wide parallel data buses between the ADC and the FPGA/ASIC. The 700 MHz input bandwidth supports undersampling of IF frequencies, simplifying receiver architectures by eliminating a downconversion stage. Typical applications include cellular base-station receivers (LTE, WCDMA, GSM), software-defined radio (SDR), digital oscilloscopes, radar and lidar systems, medical imaging, and cable modems. The combination of high input bandwidth, JESD204 output, and 16-bit resolution is well suited to multi-carrier, multi-standard communications infrastructure where dynamic range and channel density matter. When designing with this part, provide a low-jitter clock source (<200 fs RMS) to preserve SNR at high input frequencies. Decouple AVDD and DVDD supplies separately with 10uF and 0.1uF ceramic capacitors placed within 5 mm of the supply pins. Route the JESD204 serial lanes as 100 ohm differential pairs, length-matched to within 5 mils, and keep them isolated from noisy digital returns. This page synthesizes the manufacturer datasheet, real distributor pricing, JESD204 pin-compatible alternatives from the LTC226x family, and practical PCB-layout notes not found on the manufacturer's product page, giving an engineer one consolidated reference for design-in.
LTC2274CUJ - 16-Bit 105Msps JESD204 Serial ADC | Analog Devices
The Analog Devices LTC2274CUJ is a 16-bit, 105 Msps analog-to-digital converter with a high-speed JESD204 serial interface, packaged in a 40-pin QFN (6x6 mm) with exposed pad. Designed for digitizing high-frequency, wide-dynamic-range signals, it offers an analog input bandwidth of 700 MHz and an optimized input range via an integrated PGA front end. An ADC (analog-to-digital converter) is a mixed-signal integrated circuit that samples continuous analog waveforms and outputs discrete digital codes at a sample clock rate. The 16-bit resolution places the LTC2274 in the precision ADC tier, and a pipelined architecture typically delivers sustained high sample rates while keeping per-sample latency predictable. The LTC2274 specifically outputs its data via the JEDEC JESD204 serial interface, a serializer/link-layer standard that reduces board-routing congestion compared to parallel LVDS outputs. Key specifications include 16-bit resolution, 105 Msps sample rate, 700 MHz analog input bandwidth, 1 input channel, pipelined architecture, and a JESD204 serial output (replacing traditional CMOS/LVDS parallel buses). It is offered in the 40-QFN (6x6) package, lead-free (#PBF suffix), commercial temperature grade (-40C to +85C). Technically, the LTC2274 uses a multi-stage pipelined core with proprietary proprietary front-end PGA, allowing the input full-scale range to be scaled for optimum SNR vs. FSR tradeoffs. The JESD204 link supports deterministic latency and lane rates suitable for downstream FPGAs/ASICs, and the wide 700 MHz input bandwidth permits undersampling of IF/RF signals in communications systems. Typical applications include wideband communications, cellular base-station receiver IF digitizers, test and measurement instrumentation, medical imaging, defense electronics, and broadband data acquisition where JESD204 simplifies backplane routing to FPGAs. When designing the PCB, allocate a continuous ground plane under the exposed pad and stitch vias around the QFN perimeter to control switching currents from the JESD204 serializer. Decouple AVDD and DVDD rails with separate 1 uF/0.1 uF ceramic pairs, and route the JESD204 differential pairs with 100-ohm controlled impedance. This page synthesizes distributor pricing, JESD204-compatible pin-compatible alternatives, and PCB-layout guidance that complement - rather than duplicate - the manufacturer datasheet.
LTC2274IUJ - 16-Bit 105Msps Serial ADC, 40-QFN | Analog Devices
The Analog Devices LTC2274IUJ is a 16-bit, 105 Msps pipelined analog-to-digital converter with a high-speed serial (JESD204-style) output, housed in a 40-pin 6 mm × 6 mm QFN package. It is designed for digitizing high-frequency, wide-dynamic-range signals with an input bandwidth of 700 MHz and an SNR-optimized PGA front end that lets the user trade full-scale range against distortion performance. An ADC (analog-to-digital converter) is a data-converter subcategory of mixed-signal integrated circuits whose role is to sample continuous analog waveforms and produce discrete digital words at a defined sample rate. In the system hierarchy, the LTC2274IUJ sits between analog front-end signal conditioning (amplifiers, filters, transformers) and the FPGA/ASIC that consumes the digital data, placing it firmly inside the data-converter branch of the signal-chain taxonomy. Key features include 16-bit resolution at 105 Msps, 700 MHz analog input bandwidth, a programmable-gain amplifier (PGA) front end for input-range tuning, and a serialized LVDS output that minimizes pin count and simplifies PCB routing into modern FPGAs. The part shares a pin-compatible pinout across the LTC2272/LTC2273/LTC2274 family, allowing 65/80/105 Msps system scaling without PCB rework. Typical applications include basestation receivers, radar and lidar digitizers, high-end medical imaging, communications test equipment, and any wideband signal-chain that needs low-noise 16-bit conversion with a low-pin-count interface. The wide analog input bandwidth lets the same ADC digitize both baseband and IF signals after appropriate anti-alias filtering. When designing with this part, place the analog input network (transformer or driver amp) and the 40-QFN decoupling network as close as possible to the device. Use the PGA feature to optimize SFDR versus SNR for each end application, and ensure the LVDS serialization lanes are length-matched for clean FPGA capture. This page synthesizes verified distributor pricing, pin-compatible drop-in alternatives from the LTC227x family, and practical design notes not found in the manufacturer datasheet alone.
LTC2280CUP - Dual 10-Bit 105Msps Low-Noise 3V ADC | Analog Devices
The Analog Devices LTC2280CUP is a dual-channel, 10-bit, 105 Msps low-noise 3V analog-to-digital converter (ADC) housed in a 64-pin QFN (9x9 mm) package. It integrates two matched pipelined ADC cores, supports simultaneous sampling on both channels, and operates from a single 3V supply (2.85V to 3.4V), drawing approximately 250 mW total. The pipelined architecture delivers 10-bit resolution at sample rates up to 105 Msps per channel, making it well suited to intermediate-frequency (IF) digitisation in communications receivers and to dual-channel imaging systems. An ADC (analog-to-digital converter) is a mixed-signal integrated circuit that samples continuous-time analog signals and quantises them into discrete digital codes. Pipelined ADCs convert a single sample in multiple low-resolution stages, enabling high sampling rates at moderate power; within the broader taxonomy they belong to data-converter ICs, then data acquisition, then signal-chain semiconductors. The LTC2280CUP sits in the dual-channel, low-voltage, medium-resolution segment of this hierarchy. Key specifications include 61.6 dB signal-to-noise ratio (SNR) at 14 MHz input, 73 dB spurious-free dynamic range (SFDR), and an input-referred noise of 0.96 LSBrms. Each channel features its own track-and-hold amplifier, an internal reference, and a three-state digital output bus. Differential inputs are supported, and the device accepts both single-ended and differential drive topologies. Power-down, out-of-range, and data-ready indicators simplify system integration with FPGAs and DSPs. Typical applications include dual-channel digital oscilloscopes and data acquisition front-ends, IF sampling for software-defined radio (SDR) and cellular base stations, medical ultrasound beamforming arrays, and dual-stream CCD or CMOS imaging pipelines. The 3V analog supply and LVCMOS/LVDS-compatible outputs ease interface to modern low-voltage FPGAs and ASICs. When designing with this device, allocate generous ground and power planes around the 64-pin QFN exposed pad to manage thermal dissipation (about 1.2W at 105 Msps, dual channel). Use 0.1 uF ceramic bypass capacitors within 5 mm of every supply pin, and route the analog inputs as 50 ohm-controlled-impedance differential pairs to preserve SNR at the 70 MHz input bandwidth.
LTC2281CUP - Dual 10-Bit 125Msps 3V ADC | Analog Devices
The Analog Devices LTC2281CUP is a dual 10-bit 125 Msps low-power 3V analog-to-digital converter (ADC) housed in a 64-pin QFN (UP) 9x9 mm package. It delivers 61.6 dB SNR and 82 dB SFDR at the Nyquist input frequency, making it suitable for digitizing high-frequency, wide-dynamic-range signals in imaging and communications systems. The 'C' grade supports the commercial operating range of 0C to +70C. A pipelined ADC is a multi-stage converter architecture where each stage samples and produces a multi-bit residue, with stages cascaded through low-resolution flash sub-ADCs and DACs. Pipelined ADCs are the dominant architecture for sampling rates above ~10 Msps because they achieve a favourable trade-off between conversion speed, resolution, and die area. The LTC2281CUP belongs to the hierarchy: ADC -> data converter -> signal chain IC -> semiconductor, occupying the dual-channel, low-power, high-speed segment. Key features include 1.2 Vp-p or 2 Vp-p selectable input ranges, an internal 2.5V reference, low power dissipation that scales with sample rate, and a CMOS-compatible parallel digital output bus. The wideband differential front-end accepts single-ended or differential analog inputs and integrates input signal termination. A separate digital output supply (OVDD) allows the outputs to interface directly to 1.8V, 2.5V, or 3.3V logic without level translators. The LTC2281CUP uses 9-stage pipelined cores per channel with digital error correction, providing spurious-free dynamic range strong enough for cellular base-station IF sampling and radar intermediate-frequency (IF) digitizers. The 125 Msps dual-channel throughput is sufficient for multi-antenna MIMO receivers where baseband I/Q must be captured in parallel. Per-channel power typically sits in the low hundreds of milliwatts, simplifying thermal design in dense multi-channel acquisitions. Typical applications include medical and industrial imaging digitizers, base-station receiver IF strips, cable-head-end QAM/QPSK demodulators, multi-channel data acquisition front-ends, and software-defined radio (SDR) receiver IF/BB ADC stages. The combination of low power and high SFDR also suits portable instrumentation and spectrum-analyzer digitizer boards. Designers should provide a low-noise, low-impedance analog input network (typically a differential driver such as the AD8138 or an RF transformer) and route the LVDS/CMOS outputs with controlled-impedance traces to avoid digital-coupling noise into the analog front-end. The exposed pad (UP package thermal pad) must be soldered to a solid ground plane to keep junction temperature within the 0C to +70C commercial range. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet.
LTC2282CUP - Dual 12-Bit 105Msps Low Power 3V ADC | ADI
The Analog Devices LTC2282CUP is a dual 12-bit, 105 Msps low-power 3V analog-to-digital converter (ADC) housed in a 64-lead QFN (9x9 mm) package with exposed pad. It is designed for digitizing high-frequency, wide-dynamic-range signals, with AC performance that includes 70.1 dB SNR and 85 dB SFDR at the Nyquist frequency, plus ±0.4 LSB INL and ±0.3 LSB DNL (typical). An ADC (analog-to-digital converter) is a mixed-signal integrated circuit that samples continuous analog input voltages and converts each sample into a discrete digital code, forming the bridge between the analog front end and the digital signal-processing chain of a system. ADCs are positioned in the signal-conditioning hierarchy as: sensor/transducer -> analog front end -> ADC -> DSP/FPGA/microprocessor. High-speed, low-power pipelined ADCs like the LTC2282 sit at the heart of imaging, communications, and instrumentation systems where dynamic range and power budget are both critical. The LTC2282CUP uses a pipelined architecture with per-stage digital error correction, providing 12-bit resolution at sample rates up to 105 Msps. Single 3V supply operation, optional 2.5V to 3.3V logic, and an integrated low-noise reference simplify board design. The differential analog inputs support input ranges of ±0.5V to ±1V, while an internal sample-and-hold handles full-scale input bandwidths of 250 MHz or higher, enabling undersampling of IF bands. Power dissipation is typically 540 mW (per the LTC2282 datasheet 2282fb) when both channels are active at full sample rate. Typical applications include imaging and ultrasound front ends, baseband or low-IF digital receivers, cable and broadband modems, multi-channel instrumentation, and portable/wireless transceivers. The dual-channel architecture with tightly matched gain and offset also makes the part well suited to I/Q baseband sampling and diversity receivers where channel matching matters. When designing with this part, pay particular attention to the analog-input common-mode voltage, the ENC sampling-clock duty cycle (50% ±5% recommended), and the layout of the exposed thermal pad to ground. The 64-lead QFN EP must be soldered to a sufficiently large ground pour to achieve the 33 C/W theta_JA figure noted in the manufacturer datasheet. Decouple each supply pin (AVDD, DVDD, OVDD) with a 0.1 uF ceramic plus a 10 uF bulk capacitor placed within 3 mm of the pin. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet, giving engineers a faster path to a complete, qualified BOM.
LTC2282IUP - Dual 12-Bit 105Msps Low Power 3V ADC | Analog Devices
The Analog Devices LTC2282IUP is a dual 12-bit, 105Msps, low-power 3V analog-to-digital converter (ADC) designed for digitizing high-frequency, wide dynamic range signals, housed in a 64-lead QFN (UP) package measuring 9 mm × 9 mm with an exposed pad. It delivers 70.1 dB SNR and 85 dB SFDR at the Nyquist frequency, while consuming approximately 150 mW per channel from a single 3 V analog supply, and it is specified over the industrial temperature range of -40 °C to +85 °C. An ADC (analog-to-digital converter) is a mixed-signal integrated circuit that samples continuous analog voltage waveforms and converts each sample into a discrete binary code at a defined sampling rate. Within the broader taxonomy, the LTC2282 belongs to the SAR/pipelined ADC family used for communications, imaging, and instrumentation signal chains. The 12-bit resolution, 105 Msps throughput, dual-channel architecture, and 3 V low-power operation position it as a mid-resolution, high-speed converter optimized for systems where board space, channel density, and power dissipation are all critical constraints. Key features include a pipelined internal architecture with input bandwidth exceeding 250 MHz, a flexible differential or single-ended analog input with on-chip sample-and-hold, and separate analog (VA) and digital (VD) supplies that allow ground-noise isolation between sensitive analog front-end circuits and noisy digital logic. The integrated clock duty-cycle stabilizer relaxes timing requirements on the external encoder clock, and the parallel CMOS outputs simplify interface to an FPGA or DSP. The 64-pin QFN package provides low thermal resistance and an exposed pad for direct PCB heatsinking, enabling both ADCs to operate at full sampling rate without external cooling. Per the Analog Devices datasheet, typical applications include cellular basestation receive paths, medical imaging front-ends, cable modem downstream digitizers, and portable test instrumentation. Digitizers perform final signal capture after analog gain and filtering stages, and the LTC2282's wide input bandwidth simplifies anti-alias filter design. When designing with this device, separate analog and digital ground planes must meet only at the exposed pad to prevent digital switching noise from coupling into the analog inputs. A low-jitter clock source and short PCB traces to the encode input are required to preserve SNR at high input frequencies.
LTC2283CUP - Dual 12-Bit 125Msps 3V ADC | Analog Devices
The Analog Devices LTC2283CUP is a dual 12-bit, 125 Msps low-power 3V analog-to-digital converter housed in a 64-pin QFN (9x9 mm, exposed pad) package. The dual-channel pipelined architecture provides 70.1 dB SNR and 82 dB SFDR at the Nyquist frequency, with 2 channels simultaneously sampling at up to 125 Msps. The 3V analog supply operation minimizes power dissipation to approximately 400 mW per channel, while the separate digital output driver supply (OVDD) supports flexible interfacing with 1.5 V to 3.3 V logic families. The integrated input pipeline features single-ended or differential inputs, an internal sample-and-hold, and a high-bandwidth track-and-hold amplifier suitable for digitizing high-frequency signals. What is a pipeline ADC? A pipeline analog-to-digital converter (ADC) is a high-speed successive architecture that processes analog input samples through a cascade of low-resolution stages, each handling one bit (or a few bits) of conversion before passing the residue to the next stage. Pipeline ADCs balance high sampling rates (tens to hundreds of Msps) with moderate resolution (10-16 bits), making them the dominant architecture for communications baseband, IF digitization, imaging, and test equipment. They sit within the ADC taxonomy below successive-approximation (SAR) ADCs in resolution but above flash ADCs in speed/resolution trade-off. Pipeline ADCs require careful front-end driver, reference, and clock design to achieve their rated AC performance. Key features include a flexible input range (1 Vp-p to 2 Vp-p differential), internal or external voltage reference operation, and a low-jitter LVDS or CMOS-compatible output interface (selectable per device variant). The 64-lead QFN package offers excellent thermal performance and is required for the exposed thermal pad that connects to the internal ground plane. The device supports both internal and external clocking with sub-picosecond aperture jitter for IF-sampling applications. The LTC2283's dual-channel architecture, low power dissipation, and high SFDR make it well suited to multi-antenna wireless receivers, medical ultrasound beamformers, and portable test instruments. Its CMOS-compatible digital interface simplifies connection to FPGAs and DSPs without requiring level shifters. Applications include cellular basestation diversity receivers, cable head-end downstream digitizers, ultrasound imaging front ends, and spectral analysis instrumentation. The wide input bandwidth supports direct IF sampling in the 70 MHz to 140 MHz range commonly used in software-defined radio designs. Designers should pay attention to input common-mode voltage and the recommended anti-alias filter topology, which directly affects achievable SNR. A differential input driving transformer or fully differential amplifier maximizes second-harmonic distortion performance. A low-noise LDO such as the LT1763 should power the analog AVDD rail, while the OVDD rail may be driven by a digital supply if output level translation is acceptable. This page synthesizes distributor pricing, drop-in alternatives from the same LTC228x and LTC226x families, and practical PCB layout/design notes not consolidated on a single manufacturer page.
LTC2285CUP - Dual 14-Bit 125Msps Low-Power 3V ADC | ADI
The Analog Devices LTC2285CUP is a dual 14-bit, 125 Msps low-power 3V analog-to-digital converter (ADC) housed in a 64-lead QFN (9x9 mm) package, designed for digitizing high-frequency, wide dynamic range signals. It provides two simultaneous sampling channels at 125 MSPS with AC performance of 72.2 dB SNR and 82 dB SFDR at the Nyquist frequency, while consuming approximately 150 mW per channel from a single 3V supply. The device is built for demanding imaging and communications applications where low noise, wide spurious-free dynamic range, and low power are simultaneously required. A pipelined ADC is a multi-stage conversion architecture that uses a cascade of low-resolution flash stages and digital correction logic to achieve high sampling rates with moderate-to-high resolution, while consuming far less power than a full-flash converter of equivalent resolution. The LTC2285CUP sits in the product hierarchy of: ADC -> data converter -> signal chain IC -> mixed-signal semiconductor, and is a member of ADI's broad family of low-power, high-performance 3V ADCs. Key features of the LTC2285CUP include dual 14-bit 125 MSPS conversion, integrated input PGA, single 3V supply operation, low power dissipation near 235 mW total at full speed, and pin-selectable input ranges. Differential inputs with on-chip track-and-hold circuits minimize aperture jitter, and an internal duty-cycle stabilizer compensates for variations in the clock duty cycle to preserve SNR at high input frequencies. Typical applications include cellular base-station receiver IF digitizers, ultrasound imaging front ends, cable head-end digital receivers, and high-speed digital oscilloscopes. When using the LTC2285CUP, careful attention should be paid to analog input common-mode voltage and clock jitter: the SNR degrades with finite clock aperture jitter, so designers should use a low-jitter clock source and follow ADI's standard 50-ohm matched differential input network to preserve AC performance. This page synthesizes distributor pricing, drop-in same-package alternatives, and practical design notes not consolidated in the manufacturer datasheet, helping engineers shorten part selection and BOM qualification cycles.
LTC2286CUP - Dual 10-Bit 25Msps Low-Noise 3V ADC | Analog Devices
The Analog Devices LTC2286CUP is a dual 10-bit, 25 Msps, low-noise 3V analog-to-digital converter (ADC) housed in a 64-pin QFN (9x9 mm, HVQCCN) package. It delivers 61.6 dB SNR and 85 dB SFDR at a 70 MHz input, with 110 dB channel isolation at 100 MHz, while consuming only 150 mW per device from a single 3V supply. The LTC2286 is the 25 Msps member of the LTC2288/LTC2287/LTC2286 family of dual 10-bit 3V ADCs from Analog Devices. An analog-to-digital converter (ADC) is a semiconductor device that transforms continuous analog signals into discrete digital codes for processing by digital systems. Pipeline ADCs like the LTC2286 use a multistage architecture to achieve high sampling rates while keeping power and die area low, sitting between successive-approximation register (SAR) ADCs (lower speed, lower power) and flash ADCs (highest speed, highest power) in the data-converter hierarchy. Dual-channel pipeline ADCs are especially important for communications, imaging, and I/Q demodulation where two correlated channels must be digitized simultaneously with matched gain, offset, and phase. Key features include a 61.6 dB signal-to-noise ratio (SNR) and 85 dB spurious-free dynamic range (SFDR) at a 70 MHz analog input, 110 dB crosstalk isolation at 100 MHz, and flexible input ranges up to 2 V peak-to-peak. The part supports multiplexed or simultaneous sampling of the two channels, configurable via the MUX pin, and includes an internal voltage reference as well as an option for an external reference. The 64-pin exposed-pad QFN package provides a low thermal resistance path, allowing the 150 mW typical dissipation to be handled without an external heatsink. The LTC2286 uses a proprietary multi-stage pipelined architecture with proprietary SHA front-end and on-chip sample-and-hold, internal bandgap reference, and programmable output data formatting (CMOS single-ended or LVDS). The flexible digital interface simplifies connection to FPGAs and DSPs, while the input common-mode circuitry allows DC- or AC-coupled inputs with single-ended or differential drive. Typical applications include cellular base-station receivers, I/Q demodulation in software-defined radio (SDR), medical imaging front ends, CCD imaging digitizers, and low-cost digital oscilloscope input channels. The combination of dual channels, low noise, and 25 Msps speed makes it especially attractive for IF-sampling receivers in wireless infrastructure. When designing with the LTC2286CUP, ensure the analog inputs are driven with low-impedance, bandwidth-appropriate amplifiers and that the exposed pad is soldered to a sufficient copper pour for thermal dissipation. Decoupling the 3V analog and digital supplies close to the pins is critical to achieving the rated SNR/SFDR performance. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes that complement the Analog Devices datasheet, giving engineers a single reference for sourcing and selection decisions.
LTC2287CUP - Dual 10-Bit 40Msps Low Noise 3V ADC | Analog Devices
The Analog Devices LTC2287CUP is a dual 10-bit, 40 Msps low-noise 3V analog-to-digital converter (ADC) housed in a 64-pin QFN (9x9 mm) package. It integrates two matched 10-bit pipelined ADC cores with 61.6 dB SNR and 85 dB SFDR at a 70 MHz analog input, delivering imaging-quality digitisation for communications, IF-sampling, and multi-channel instrumentation front ends. An analog-to-digital converter (ADC) is a mixed-signal integrated circuit that samples a continuous-time analog voltage and produces a discrete-time digital code representing the input level. Pipelined ADCs use a cascade of low-resolution stages with inter-stage residue amplifiers to achieve high sample rates at moderate power, and dual-channel variants like the LTC2287CUP share a common reference and clock network to guarantee tight gain and offset matching between channels - critical for I/Q baseband, diversity receivers, and medical beamforming. Key specifications include 3V single-supply operation (2.85V to 3.4V), 235 mW total power dissipation at 40 Msps, 110 dB channel-to-channel isolation at 100 MHz, and selectable multiplexed or simultaneous-sampling operation. The differential inputs accept 1 Vp-p full-scale swings, and the parallel CMOS outputs are easily routed to FPGAs or DSPs with 3V LVCMOS logic. Optional duty-cycle stabiliser and internal reference are factory-trimmed to remove external component count. The pipelined architecture provides 1.5 clock-cycle latency and supports a 1 to 40 Msps sample-rate window via the CLOCK duty-cycle control pin. Independent shutdown pins reduce per-channel power in time-division applications, and the 64-lead QFN exposed-pad package delivers the thermal performance required for full-rate operation across the 0C to 70C commercial temperature range without derating. Typical applications include cellular base-station receivers, ultrasound imaging front ends, multi-carrier software-defined radio (SDR) platforms, low-cost oscilloscope channels, and instrumentation digitiser cards. Designers choose the LTC2287CUP when dual-channel 10-bit precision at 40 Msps is needed in a compact, low-power footprint. For best results, route differential analog inputs as 50 ohm controlled-impedance pairs and place 0.1 uF bypass capacitors adjacent to each supply pin. Confirm that the FPGA timing budget accommodates the 1.5-cycle pipeline latency and that the digital outputs are not loaded above 10 pF per pin to preserve SNR. This page synthesises distributor pricing, pin-compatible alternatives in the same 64-QFN footprint, and practical design notes not found in the standalone manufacturer datasheet, helping engineers shorten the selection cycle.
LTC2288CUP - Dual 10-Bit 65Msps Low-Noise 3V ADC | Analog Devices
The Analog Devices LTC2288CUP is a dual 10-bit, 65Msps low-noise 3V analog-to-digital converter (ADC) housed in a 64-pin QFN (9x9 mm) exposed-pad package. It digitizes two simultaneous channels at up to 65 million samples per second per channel from a single 3V analog supply, with a typical SNR of 61.6 dB and SFDR of 78 dB at the 65Msps rate, and supports both single-ended and differential input configurations. An ADC (analog-to-digital converter) is a mixed-signal integrated circuit that samples a continuous analog input voltage and converts it into a discrete digital code, typically for downstream processing by an FPGA, DSP, or microcontroller. The LTC2288 belongs to the pipelined-ADC class, the dominant architecture for sampling rates between 1Msps and 250Msps, where multiple low-resolution flash stages are cascaded to produce the final 10-bit code at high speed. Within the broader taxonomy, ADCs sit inside the data-converter family alongside DACs, and data converters are a subset of mixed-signal ICs and ultimately semiconductors. Key features of the LTC2288CUP include 65Msps/40Msps/25Msps speed grades selectable by part number, pin-compatible with the LTC2287 (40Msps) and LTC2286 (25Msps), a flexible differential or single-ended analog input front end, integrated input PGA, on-chip reference, and a low-voltage CMOS-compatible parallel digital output bus. The 3V single-supply operation reduces power dissipation to roughly 150 mW per channel at full speed, and the exposed-pad QFN-64 package provides a low thermal resistance of about 28 C/W for reliable operation at the upper commercial temperature limit. The pipelined architecture uses 8 cascaded 1.5-bit stages with a backend flash for the LSBs and a proprietary digital error-correction block that guarantees no missing codes at the full 10-bit resolution. This combination delivers excellent spurious-free dynamic range across the Nyquist band, making the part well-suited to wide-bandwidth signal chains. Typical applications include high-end CCD imaging, ultrasound beamforming front ends, cellular base-station IF digitizers, and communications test equipment. Design considerations include providing a low-jitter encode clock, decoupling the analog and digital supplies separately, and tying the exposed pad to a clean analog ground plane.
LTC2288IUP - Dual 10-Bit 65Msps 3V ADC | Analog Devices
The Analog Devices LTC2288IUP is a dual 10-bit, 65Msps, low-noise 3V analog-to-digital converter (ADC) housed in a 64-pin QFN (9x9 mm) package with exposed pad. The IUP suffix denotes the industrial temperature grade (-40C to +85C), and the device features two fully differential pipelined ADC channels designed for digitizing wide dynamic range signals at low power. The LTC2288 is one of three speed grades (65Msps/40Msps/25Msps) in the LTC2286/LTC2287/LTC2288 family sharing an identical pinout. A pipelined ADC is a multi-stage converter architecture that processes one sample per clock cycle after an initial pipeline delay, achieving high sampling rates while consuming moderate power. Pipelined ADCs sit within the broader ADC taxonomy (flash > folding > pipelined > SAR > sigma-delta), offering the best speed-resolution trade-off for 8-bit to 14-bit IF/baseband sampling in communications, imaging, and instrumentation. Dual-channel devices such as the LTC2288IUP are commonly used for I/Q baseband digitization where matched channel performance is critical. Key features include 10-bit resolution, 65Msps sample rate, 3V single supply operation (2.85V to 3.4V), 61dB SNR at 14MHz input, and an integrated digital error correction engine. The device supports both single-ended and differential input configurations, with input bandwidth exceeding 250MHz. The 64-QFN package provides a low thermal-resistance path via the exposed pad for reliable operation across the industrial temperature range. The LTC2288IUP is well-suited for cellular base station receivers, digital predistortion feedback paths, IF sampling in software-defined radios, medical imaging front-ends, and high-speed data acquisition modules. Its dual matched channels simplify I/Q demodulation and reduce board area by integrating two converters into one package. When designing with the LTC2288IUP, provide a low-impedance analog ground plane and stitch the exposed pad with multiple vias to a ground pour to minimize thermal and noise coupling. A 0.1uF bypass capacitor placed within 2mm of each supply pin and a clean low-noise 3V LDO (such as the LT1761) feeding AVDD ensures rated SNR performance is achieved. This page synthesizes distributor pricing, drop-in 64-QFN alternatives, and application guidance not found on standard distributor listings, providing a single engineering reference for the LTC2288IUP.
LTC2290IUP - Dual 12-Bit 10Msps Low Power 3V ADC | ADI
The Analog Devices LTC2290IUP is a dual 12-bit, 10Msps low-power 3V analog-to-digital converter (ADC) housed in a 64-pin QFN (9x9 mm) package, designed for digitizing high-frequency, wide-dynamic-range signals with 71.3 dB SNR and 90 dB SFDR. Operating from a single 3V supply, the device integrates two matched sample-and-hold channels and a pipelined architecture to deliver AC performance that holds well beyond the Nyquist frequency. An ADC (analog-to-digital converter) is a mixed-signal data-conversion IC that samples a real-world analog waveform and outputs a discrete multi-bit digital code, forming the bridge between the analog sensor/frontend domain and the digital signal-processing domain. ADCs sit inside the broader signal chain hierarchy: analog front end -> ADC -> digital signal processor (DSP/FPGA/microcontroller). Within the ADC family, the LTC2290 is a successive-approximation/pipelined SAR-pipeline hybrid optimized for high-speed IF sampling with low power consumption, a profile that places it in the data-converter IC category alongside other precision converters. Key features include 71.3 dB signal-to-noise ratio (SNR), 90 dB spurious-free dynamic range (SFDR), and ultralow crosstalk between the two ADC channels for simultaneous sampling applications. The integrated input sample-and-hold amplifier accepts single-ended or differential inputs and supports input frequencies up to and beyond the Nyquist limit, making the device suitable for undersampling IF architectures used in communications receivers. Typical applications include imaging systems, communications receivers requiring IF sampling, basestation quadrature demodulation, and portable instrumentation. The wide spurious-free dynamic range preserves signal integrity in dense spectrum environments, while the low 3V power consumption makes the part attractive for power-constrained designs. When designing with the LTC2290IUP, ensure the analog input common-mode voltage sits within the specified range and use the on-chip reference or an external low-impedance reference for optimal linearity.
LTC2291IUP - Dual 12-Bit 25Msps Low-Power 3V ADC | Analog Devices
The Analog Devices LTC2291IUP is a dual 12-bit, 25 Msps, low-power 3V analog-to-digital converter supplied in a 64-pin QFN (9x9) package with industrial temperature grade (-40C to +85C). The device integrates two matched 12-bit pipeline ADCs on a single die and supports simultaneous sampling of two analog channels, making it suitable for I/Q baseband, diversity receivers, and multi-channel imaging front-ends where board real-estate is limited. An ADC (Analog-to-Digital Converter) is a mixed-signal integrated circuit that samples a continuous analog input voltage and produces a discrete digital code proportional to that input. Pipeline ADCs in particular use a multi-stage architecture with per-stage flash sub-ADCs and DACs to achieve high sample rates (tens to hundreds of Msps) at moderate resolution (10-14 bits) while keeping power dissipation low - they sit in the converter hierarchy between flash (highest speed, lowest resolution) and sigma-delta (highest resolution, lowest speed). The dual-channel LTC2291 occupies the lower-power end of the 25 Msps class, drawing roughly 1.5W per channel. Key features of the LTC2291IUP include 71.3 dB SNR and 90 dB SFDR at the Nyquist input frequency, differential input architecture for excellent common-mode noise rejection, selectable input ranges of ±1V or ±0.5V around a common-mode level near 2V, and a flexible LVDS/CMOS output interface. The device operates from a single 2.85V-3.3V analog supply, includes an internal reference, and offers an optional external reference mode for gain accuracy. Typical applications for the LTC2291 include communications receivers (cellular base-station I/Q digitizers), medical imaging (ultrasound beamforming front-ends), high-end instrumentation (digital oscilloscopes and spectrum analyzers), and defense/multimedia systems. The combination of low power and dual-channel density also makes it a frequent choice for handheld test equipment. When designing with this part, pay special attention to analog input common-mode biasing and decoupling - the LTC2291 requires AC-coupling or DC bias networks on each input, and ground-bounce on the analog supply can couple directly into the sample clock jitter. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet.
LTC2292CUP - Dual 12-Bit 40Msps 3V ADC | Analog Devices
The Analog Devices LTC2292CUP is a dual 12-bit, 40 Msps low-power 3V analog-to-digital converter (ADC) housed in a 64-pin QFN (UP, 9x9 mm) exposed-pad package. It integrates two independent 12-bit pipelined ADC channels on a single die, each sampling at up to 40 million samples per second while consuming only 235 mW of total power from a single 3V supply (2.5V to 3.4V). The part delivers 71.3 dB SNR and 85 dB SFDR for input tones up to 70 MHz, making it well suited for digitizing wide dynamic range IF signals. What is a dual ADC? A dual analog-to-digital converter combines two matched ADC channels on one IC so that the system can digitize two analog inputs simultaneously. The LTC2292CUP belongs to the ADC family (analog-to-digital converter) -> data converter -> signal chain IC -> mixed-signal semiconductor. Each internal channel uses a pipelined multi-stage architecture that converts input samples in successive stages; this trades a small fixed latency for high sampling rates at low power, which is the standard approach for communications, imaging, and instrumentation front ends. Key features include simultaneous sampling on two channels, a flexible CMOS or LVDS digital output interface, a multiplexed (MUX) output mode that puts both channels on one bus, and selectable input ranges of 1 Vp-p or 2 Vp-p. The device also provides 110 dB channel-to-channel isolation at 100 MHz, internal duty-cycle stabilized clock generation that accepts any duty cycle from 20% to 80%, and a shutdown/power-down pin for portable applications. The exposed thermal pad of the QFN-64 package gives a theta_JA around 28 C/W with proper PCB layout, enabling 235 mW operation without a heatsink. Typical applications include cellular basestation receiver IF digitizers, portable ultrasound imaging front ends, spectrum analyzer and digital oscilloscope input stages, cable-headend downstream tuners, and multi-channel data acquisition boards for industrial inspection. The wide 70 MHz input bandwidth and high SFDR also make it appropriate for software-defined radio (SDR) and digital pre-distortion feedback paths in RF power amplifier linearization. When designing with the LTC2292CUP, route analog inputs as 50 ohm controlled-impedance traces with 100 ohm differential terminations when driving the inputs differentially, and stitch the exposed pad (EP) with at least 9 thermal vias to the inner ground plane. A low-noise LDO such as the ADP3338 should supply AVDD, and unused digital outputs may be left floating or three-stated via the OE pin.
LTC2292IUP - Dual 12-Bit 40Msps 3V ADC | Analog Devices
The Analog Devices LTC2292IUP is a dual 12-bit, 40 Msps low-power 3V analog-to-digital converter housed in a 64-pin QFN (9x9 mm) package with exposed thermal pad. It accepts two differential input channels and delivers 12-bit resolution at sample rates up to 40 Msps, making it suitable for digitizing high-frequency, wide-dynamic-range signals in imaging and communications systems. The converter is part of the LTC2293/LTC2292/LTC2291 family, which scales sampling rate (65/40/25 Msps) while sharing pinout and digital interface, simplifying multi-speed platform designs. An analog-to-digital converter (ADC) is a mixed-signal integrated circuit that samples continuous analog voltage waveforms and quantizes each sample into a discrete binary code, bridging the analog and digital domains in modern electronic systems. The LTC2292IUP belongs to the pipelined ADC subclass, which uses a multi-stage switched-capacitor architecture to achieve high sampling rates (>10 Msps) with moderate power consumption. In the broader component taxonomy, it sits as: ADC -> data converter -> mixed-signal IC -> semiconductor. Pipelined ADCs trade slightly higher latency for high throughput, and are the dominant architecture in communications infrastructure, imaging, and instrumentation front-ends. Key features of the LTC2292IUP include 71.3 dB SNR and 90 dB SFDR at the Nyquist input frequency, ensuring high spurious-free dynamic range critical for multi-carrier communications and spectral analysis. The part operates from a single 3V supply (2.85V to 3.4V), consumes approximately 120 mW per channel at 40 Msps, and supports an optional low-power shutdown mode. Its 64-lead QFN (9x9) package provides an exposed pad for low thermal resistance, enabling sustained operation in space-constrained designs without external heatsinking. The integrated input sample-and-hold and internal reference simplify external BOM, while the LVDS-compatible digital outputs (configurable in CMOS/CMOS-low-power modes) ease interface to FPGAs and DSPs. Typical applications include cellular basestation IF digitizers, ultrasound imaging receivers, portable instrumentation, and software-defined radio front-ends. The wide spurious-free dynamic range of 90 dB makes the LTC2292IUP especially attractive in scenarios where strong interferers must be rejected while small signals are captured, such as in dense multi-channel spectrum analysis or multi-carrier base-station receivers. Combined with the family scalability, designers can use the LTC2291/2292/2293 to cover a 25-65 Msps range with a single PCB layout, simplifying platform variants. When designing with the LTC2292IUP, use a low-impedance ground plane beneath the package, bypass the analog supply (pins 11/12) with both 0.1 µF and 2.2 µF ceramic capacitors placed as close to the pins as possible, and a 1 µF capacitor to ground near the reference pin. Drive the analog inputs with a low-noise differential amplifier to fully realize the 71.3 dB SNR; mismatched input amplitudes will degrade SFDR. The exposed pad must be soldered to a sufficient copper pour to keep the junction temperature within the -40°C to +85°C industrial operating range. This page synthesizes distributor stock and pricing, drop-in same-family alternatives, and practical design considerations (input driving, supply bypassing, thermal layout) not consolidated on the manufacturer product page.
LTC2293CUP - Dual 12-Bit 65Msps Low Power 3V ADC | Analog Devices
The Analog Devices LTC2293CUP is a dual 12-bit, 65 Msps, low-power 3V analog-to-digital converter housed in a 64-pin QFN (9x9 mm) package with exposed pad. It integrates two matched 12-bit pipelined ADC channels that sample simultaneously at up to 65 Msps while consuming approximately 120 mW per channel from a single 3V supply. The device achieves 71.3 dB SNR and 90 dB SFDR at the Nyquist input frequency, satisfying demanding imaging and communications signal-chain requirements. A pipelined ADC (pipelined analog-to-digital converter) is a multi-stage converter architecture that processes the analog input through successive low-resolution flash sub-ADC stages, with each stage driving an inter-stage DAC and residue amplifier. Pipelined ADCs are favored for high sample rates (10 Msps to >1 Gsps) and resolutions from 8 to 16 bits because they balance speed, latency, and active power far better than flash or successive-approximation architectures. In the broader signal-chain taxonomy, a pipelined ADC sits below sigma-delta ADCs (which dominate high-resolution low-bandwidth instrumentation) and above general-purpose SAR ADCs (which serve kilounit-per-second precision measurements). LTC2293CUP therefore occupies the communications-and-imaging niche where 12-bit resolution and 65 Msps are jointly required. Key features include two simultaneously-sampling 12-bit ADC channels, an internal 2.5V reference that can be overdriven by an external reference via the SENSE pin, separate analog input (VA) and digital output (VD) supplies for noise isolation, and an exposed thermal pad that lowers junction-to-board thermal resistance. The differential input architecture supports single-ended or differential drive with input common-mode centered around 1.5V, simplifying interface to IF-stages, baseband filters, and CCD/CIS analog front-ends. The LTC2293CUP supports high-impedance CMOS-compatible outputs and configurable full-scale range. The 64-lead QFN (9x9 mm) footprint matches the LTC2292/LTC2291 (40 Msps / 25 Msps) and is pin-compatible with the LTC2221 family, allowing system designers to scale sampling rate by simply substituting the ADC without re-laying-out the PCB. Typical applications include cellular base-station receiver IF digitizers, ultrasound imaging arrays, cable-headend QAM/QPSK demodulators, CCD/CIS imaging pipelines, portable instrumentation, and multi-channel data-acquisition cards for industrial inspection. In each of these use cases, the LTC2293CUP's combination of dual channels, 12-bit resolution, and 65 Msps sample rate cuts board area, BOM cost, and software complexity versus two discrete single-channel ADCs. When designing with the LTC2293CUP, separate analog and digital ground planes and stitch them only under the IC's exposed pad to prevent digital switching noise from coupling back into the analog input. Use short, matched-length differential traces from the input driver to keep aperture-delay mismatch below 0.3 LSB at full clock rate. This page synthesizes distributor stock and pricing across DigiKey, Mouser, and Octopart, pin-compatible LTC2293/LTC2292/LTC2291 family drop-ins, and PCB-layout design notes that go beyond the manufacturer datasheet to help engineers shortlist a replacement or build a dual-channel 65 Msps acquisition front end on a 9x9 mm footprint.
LTC2294CUP - Dual 12-Bit 80Msps 3V ADC | Analog Devices
The Analog Devices LTC2294CUP is a dual 12-bit, 80 Msps low-power 3V analog-to-digital converter (ADC) housed in a 64-lead QFN (UP) 9x9 mm package with exposed pad. It integrates two 12-bit pipelined ADC channels that can be clocked up to 80 Msps from a single 3V supply (2.7V to 3.4V), drawing only 422 mW of total power. The device is offered in commercial (0C to +70C) temperature grade and supports both multiplexed and separate data bus modes for flexible downstream FPGA or ASIC interfacing. An ADC (analog-to-digital converter) is a mixed-signal integrated circuit that samples continuous analog voltages and outputs discrete digital codes at a fixed sampling rate. Pipelined ADCs, the architecture used in the LTC2294, cascade multiple low-resolution flash stages to achieve high sample rates (tens of Msps and above) with moderate power consumption and small die area. This makes them the dominant architecture for communications, imaging, and instrumentation applications requiring conversion of IF or baseband signals in the 1-100 MHz range. Key specifications include 70.6 dB SNR and 90 dB SFDR at 70 MHz input, ±0.4 LSB INL (typical), ±0.2 LSB DNL (typical), 110 dB channel isolation at 100 MHz, and a flexible input range of 1 Vp-p to 2 Vp-p. Optional internal dither is provided to improve SFDR when the input approaches full-scale and the spectrum would otherwise exhibit integral non-linearity spurs. A separate output supply pin permits the digital outputs to drive 3V, 2.5V, or 1.8V logic without level shifters. Typical applications include cellular base-station IF sampling, multi-channel imaging arrays, portable test and measurement front-ends, ultrasound beamformers, and low-cost digital oscilloscope input channels. The combination of dual channels and low power also suits multi-antenna diversity receivers in software-defined radio. When designing with this part, allocate the exposed pad directly under the package to a continuous ground pour and stitch it with at least 9 thermal vias to the inner ground plane. Drive the analog inputs with a low-impedance differential buffer (such as the AD8138 or AD8352) and bypass both AVDD and OVDD pins with 0.1uF ceramic capacitors placed within 2 mm of each pin. This page aggregates distributor pricing, drop-in LTC22xx/LTC23xx family alternatives, and PCB/thermal design guidance not present in the manufacturer datasheet, providing information gain beyond stock parametric listings.
LTC2295CUP - Dual 14-Bit, 10Msps Low Power 3V ADC | Analog Devices
The Analog Devices LTC2295CUP is a dual 14-bit, 10 Msps low-power 3V analog-to-digital converter (ADC) housed in a 64-pin QFN (9x9 mm) package with exposed pad. It integrates two complete 14-bit pipelined ADC channels, supports single 3V supply operation, and delivers 74.4 dB SNR and 90 dB SFDR for high-frequency signal digitization. Typical power consumption is 120 mW at full 10 Msps throughput, and the -CUP suffix denotes the commercial 0C to +70C operating temperature grade. A pipelined ADC is a high-speed analog-to-digital converter architecture that processes the analog input through multiple low-resolution stage converters, then digitally corrects the result to produce a high-resolution output. This architecture enables sample rates in the tens to hundreds of megasamples per second while maintaining low power consumption. Within the broader signal chain hierarchy, a pipelined ADC sits between successive-approximation register (SAR) ADCs (which trade speed for power) and flash ADCs (which trade resolution for speed). The LTC2295CUP specifically targets the dual-channel, mid-speed, low-power segment used in communications infrastructure, imaging, and portable instrumentation. Key performance features include 575 MHz full-power input bandwidth sample-and-hold, 110 dB channel-to-channel isolation, and a flexible input range up to 2 Vp-p. The device accepts a single-ended or differential analog input, supports multiplexed or separate data buses, and provides CMOS-compatible digital outputs. The integrated dual-channel architecture eliminates the need for two separate ADC ICs, saving board space and simplifying clock routing in multi-channel data-acquisition systems. The LTC2295CUP is built on a BiCMOS process and uses a multi-stage pipelined architecture with digital error correction to achieve its 14-bit linearity. The wide input bandwidth (575 MHz) significantly exceeds the Nyquist frequency for 10 Msps operation, allowing AC performance to be maintained well beyond the first Nyquist zone - critical for undersampling IF signals in communications receivers. The architecture includes internal references and timing circuits, reducing external component count. Typical applications include cellular base-station IF digitizing, ultrasound imaging front-ends, portable instrumentation, low-power radar signal acquisition, and dual-channel data acquisition systems. The combination of low power (120 mW), dual channels, and high AC performance makes the LTC2295CUP particularly suitable for handheld or battery-powered test equipment where dual-channel capability is required. Designers should note that the LTC2295CUP requires careful analog input network design (typically a transformer-driver or op-amp driver with anti-alias filter) to fully realize the 74.4 dB SNR. The exposed pad must be soldered to the PCB ground plane for thermal dissipation and electrical performance. The CLK input requires a low-jitter source to maintain SNR at high input frequencies. This page synthesizes distributor pricing from DigiKey and Mouser, drop-in same-package alternatives from the LTC22xx family, and practical design notes not found in the standalone manufacturer datasheet.