LTC2294CUP - Dual 12-Bit 80Msps 3V ADC | Analog Devices
部品番号: LTC2294CUP ✓ 生産中| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $49.5 | $49.50 |
| 10 | $45.2 | $452.00 |
| 100 | $41.8 | $4,180.00 |
| 500 | $40.85 | $20,425.00 |
| 1,000 | $40.85 | $40,850.00 |
LTC2294CUP 概要
An ADC (analog-to-digital converter) is a mixed-signal integrated circuit that samples continuous analog voltages and outputs discrete digital codes at a fixed sampling rate. Pipelined ADCs, the architecture used in the LTC2294, cascade multiple low-resolution flash stages to achieve high sample rates (tens of Msps and above) with moderate power consumption and small die area. This makes them the dominant architecture for communications, imaging, and instrumentation applications requiring conversion of IF or baseband signals in the 1-100 MHz range.
Key specifications include 70.6 dB SNR and 90 dB SFDR at 70 MHz input, ±0.4 LSB INL (typical), ±0.2 LSB DNL (typical), 110 dB channel isolation at 100 MHz, and a flexible input range of 1 Vp-p to 2 Vp-p. Optional internal dither is provided to improve SFDR when the input approaches full-scale and the spectrum would otherwise exhibit integral non-linearity spurs. A separate output supply pin permits the digital outputs to drive 3V, 2.5V, or 1.8V logic without level shifters.
Typical applications include cellular base-station IF sampling, multi-channel imaging arrays, portable test and measurement front-ends, ultrasound beamformers, and low-cost digital oscilloscope input channels. The combination of dual channels and low power also suits multi-antenna diversity receivers in software-defined radio.
When designing with this part, allocate the exposed pad directly under the package to a continuous ground pour and stitch it with at least 9 thermal vias to the inner ground plane. Drive the analog inputs with a low-impedance differential buffer (such as the AD8138 or AD8352) and bypass both AVDD and OVDD pins with 0.1uF ceramic capacitors placed within 2 mm of each pin.
This page aggregates distributor pricing, drop-in LTC22xx/LTC23xx family alternatives, and PCB/thermal design guidance not present in the manufacturer datasheet, providing information gain beyond stock parametric listings.
ドロップイン代替品: LTC2294CUP — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: LTC2294CUP （同一形状・フットプリント） — 相違点: Operating Temperature, Package, Power Dissipation, SNR, RoHS Status.
クイック比較ツール — 並列比較する代替部品を選択:
LTC2294IUP
✅ ドロップイン📋 参考代替品（カタログ未掲載）
LTC2294CUP#PBF
✅ ドロップイン📋 参考代替品（カタログ未掲載）
LTC2294CUP#TRPBF
✅ ドロップイン📋 参考代替品（カタログ未掲載）
LTC2292CUP
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$13.42 / 個
データシートを見る →LTC2287CUP
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$7.05 / 個
データシートを見る →LTC2282CUP
✅ ドロップイン ⚠️ 仕様未検証✓ 在庫あり
$18.5 / 個
データシートを見る →LTC2294CUP 最大定格＆電気的特性
| 分解能 | 12 bits |
| Number of Channels | 2 (dual, simultaneous sampling) |
| Sampling Rate (max) | 80 Msps |
| Architecture | Pipelined |
| Supply Voltage (AVDD) | 2.7 V to 3.4 V (single 3V supply) |
| Output Supply (OVDD) | 1.8 V / 2.5 V / 3 V selectable |
| Power Dissipation | 422 mW (typical, both channels, 80 Msps) |
| SNR | 70.6 dB at 70 MHz input |
| SFDR | 90 dB at 70 MHz input |
| INL | +/-0.4 LSB typical |
| DNL | +/-0.2 LSB typical |
| Channel Isolation | 110 dB at 100 MHz |
| Input Range | 1 Vp-p to 2 Vp-p (flexible) |
| Data Bus Mode | Multiplexed or separate (2x/1x clock options) |
| 動作温度 | 0C to +70C (commercial, C grade) |
| パッケージ | 64-pin QFN (UP) 9x9 mm with exposed pad |
| Internal Dither | Optional (improves SFDR at near-FS) |
| RoHS ステータス | Compliant (#PBF suffix) |
| 1ku List Price (LTC2294 family, starting) | $40.85 |
LTC2294CUP ピン構成
| ピン 1 | AIN1A+ — Channel 1 analog input positive |
| ピン 2 | AIN1A- — Channel 1 analog input negative |
| ピン 3 | SENSE1 — Channel 1 reference/programming |
| ピン 4 | VCM1 — Channel 1 input common-mode voltage |
| ピン 5 | REFT1 — Channel 1 top reference decoupling |
| ピン 6 | REFB1 — Channel 1 bottom reference decoupling |
| ピン 7 | VD1 — Channel 1 analog supply decoupling |
| ピン 8 | GND1 — Channel 1 analog ground |
| ピン 9 | AIN1B+ — Channel 1 second ADC input positive |
| ピン 10 | AIN1B- — Channel 1 second ADC input negative |
| ピン 11 | NC — Not connected (per datasheet) |
| ピン 12 | DITH1 — Channel 1 dither control |
| ピン 13 | AVDD — Analog 3V supply |
| ピン 14 | AGND — Analog ground |
| ピン 15 | VREF — Internal reference decoupling |
| ピン 16 | VREFT — Top reference decoupling |
| ピン 17 | VREFB — Bottom reference decoupling |
| ピン 18 | REFT2 — Channel 2 top reference decoupling |
| ピン 19 | REFB2 — Channel 2 bottom reference decoupling |
| ピン 20 | GND2 — Channel 2 analog ground |
| ピン 21 | VD2 — Channel 2 analog supply decoupling |
| ピン 22 | DITH2 — Channel 2 dither control |
| ピン 23 | NC — Not connected (per datasheet) |
| ピン 24 | SENSE2 — Channel 2 reference/programming |
| ピン 25 | VCM2 — Channel 2 input common-mode voltage |
| ピン 26 | AIN2A+ — Channel 2 analog input positive |
| ピン 27 | AIN2A- — Channel 2 analog input negative |
| ピン 28 | AIN2B+ — Channel 2 second ADC input positive |
| ピン 29 | AIN2B- — Channel 2 second ADC input negative |
| ピン 30 | NC — Not connected (per datasheet) |
| ピン 31 | OVDD — Output driver supply |
| ピン 32 | OGND — Output driver ground |
| ピン 33 | CLKOUT — Clock output for latching data |
| ピン 34 | OF — Output format select |
| ピン 35 | ENC+ — Encode clock positive input |
| ピン 36 | ENC- — Encode clock negative input |
| ピン 37 | OGND — Output driver ground |
| ピン 38 | OVDD — Output driver supply |
| ピン 39 | DA0 — Channel 2 data output bit 0 |
| ピン 40 | DA1 — Channel 2 data output bit 1 |
| ピン 41 | DA2 — Channel 2 data output bit 2 |
| ピン 42 | DA3 — Channel 2 data output bit 3 |
| ピン 43 | DA4 — Channel 2 data output bit 4 |
| ピン 44 | DA5 — Channel 2 data output bit 5 |
| ピン 45 | DA6 — Channel 2 data output bit 6 |
| ピン 46 | DA7 — Channel 2 data output bit 7 |
| ピン 47 | DA8 — Channel 2 data output bit 8 |
| ピン 48 | DA9 — Channel 2 data output bit 9 |
| ピン 49 | DA10 — Channel 2 data output bit 10 |
| ピン 50 | DA11 — Channel 2 data output bit 11 (MSB) |
| ピン 51 | DB0 — Channel 1 data output bit 0 |
| ピン 52 | DB1 — Channel 1 data output bit 1 |
| ピン 53 | DB2 — Channel 1 data output bit 2 |
| ピン 54 | DB3 — Channel 1 data output bit 3 |
| ピン 55 | DB4 — Channel 1 data output bit 4 |
| ピン 56 | DB5 — Channel 1 data output bit 5 |
| ピン 57 | DB6 — Channel 1 data output bit 6 |
| ピン 58 | DB7 — Channel 1 data output bit 7 |
| ピン 59 | DB8 — Channel 1 data output bit 8 |
| ピン 60 | DB9 — Channel 1 data output bit 9 |
| ピン 61 | DB10 — Channel 1 data output bit 10 |
| ピン 62 | DB11 — Channel 1 data output bit 11 (MSB) |
| ピン 63 | OVDD — Output driver supply |
| ピン 64 | OGND — Output driver ground |
主な用途
LTC2294CUP の用途: 6 件s: Cellular Base-Station IF Sampling, Multi-Channel Imaging Arrays, Portable Test and Measurement Front-Ends, Ultrasound Beamforming Receivers, Software-Defined Radio Diversity Receivers, Low-Cost Digital Oscilloscope Input Channel.
Cellular Base-Station IF Sampling
The LTC2294CUP is well matched to intermediate-frequency (IF) sampling in cellular base-station receivers because its 80 Msps per-channel rate digitizes 70 MHz IF signals with significant margin above the Nyquist limit while preserving 70.6 dB SNR. Two simultaneous channels on one die reduce board area versus two discrete ADCs and eliminate channel-to-channel gain/offset mismatch. Reference: LTC2294 datasheet 2294fa communications section.
おすすめ
Multi-Channel Imaging Arrays
For CCD/CIS image sensor front-ends, the LTC2294CUP samples two channels simultaneously at 80 Msps with 110 dB channel isolation, which suppresses crosstalk from the adjacent pixel channel. The 422 mW total power keeps 4-channel and 8-channel arrays within manageable thermal envelopes. According to LTC2294 datasheet 2294fa, the dither option improves SFDR when the input approaches the full-scale rail.
おすすめ
Portable Test and Measurement Front-Ends
Handheld oscilloscopes and spectrum analyzers benefit from the LTC2294CUP's 70.6 dB SNR and 80 Msps combined with 422 mW total power. Two channels at one IC halve the PCB area of the analog front-end, which is critical for compact portable enclosures. The exposed pad on the 64-pin QFN dissipates heat directly into the chassis ground plane, eliminating a discrete heatsink.
おすすめ
Ultrasound Beamforming Receivers
The dual simultaneous 80 Msps channels of the LTC2294CUP allow two adjacent transducer elements to be digitized on the same clock edge, supporting analog beamformer I/Q demodulation chains. With 70.6 dB SNR the device preserves 12-bit dynamic range required for B-mode ultrasound imaging. Reference: LTC2294 datasheet 2294fa medical imaging typical application.
おすすめ
Software-Defined Radio Diversity Receivers
Multi-antenna diversity receivers digitize two RF chains simultaneously; the LTC2294CUP's dual channels and 110 dB isolation at 100 MHz prevent one antenna's signal from leaking into the other. The 80 Msps rate supports direct sampling of IF outputs from low-IF tuner ICs. Per LTC2294 datasheet 2294fa, the multiplexed bus mode halves the FPGA pin count when a small device is targeted.
おすすめ
Low-Cost Digital Oscilloscope Input Channel
The LTC2294CUP delivers 70.6 dB SNR (about 11.5 effective bits) at 80 Msps, sufficient for entry-level 200 MHz bandwidth oscilloscope input channels. Two channels per IC support 2-channel entry products without a second ADC. The exposed pad 64-pin QFN package allows direct PCB-mounting into a scope's main board with no heatsink.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: LTC2294CUP — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | LTC2294IUP | LTC2294CUP#PBF | LTC2294CUP#TRPBF | LTC2292CUP | LTC2287CUP | LTC2282CUP |
|---|---|---|---|---|---|---|---|
| Package | 64-pin QFN (UP) 9x9 mm | 64-pin QFN (UP) 9x9 mm | 64-pin QFN (UP) 9x9 mm | 64-pin QFN (UP) 9x9 mm | 64-pin QFN (UP) 9x9 mm | 64-pin QFN (UP) 9x9 mm | 64-pin QFN (UP) 9x9 mm |
| Brand | Analog Devices (Linear Tech) | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices | Analog Devices |
| Resolution | 12 bits | 12 bits | 12 bits | 12 bits | 12 bits | 12 bits | 12 bits |
| Channels | 2 (dual) | 2 | 2 | 2 | 2 | 2 | 1 |
| Sample Rate (max) | 80 Msps | 80 Msps | 80 Msps | 80 Msps | 40 Msps | 10 Msps | 105 Msps |
| SNR (at 70 MHz) | 70.6 dB | 70.6 dB | 70.6 dB | 70.6 dB | 71.0 dB | 70.0 dB | 70.5 dB |
| Power Dissipation | 422 mW | 422 mW | 422 mW | 422 mW | 200 mW | 230 mW | 640 mW |
| Temperature Grade | 0C to +70C (Commercial) | -40C to +85C (Industrial) | 0C to +70C | 0C to +70C | 0C to +70C | 0C to +70C | 0C to +70C |
主な差別化要因
- Dual simultaneous 80 Msps channels on a single 3V supply （vs LTC2208IUP)
- Pin-compatible family spanning 10 to 105 Msps （vs LTC2287CUP)
- 110 dB channel isolation at 100 MHz （vs Generic dual ADC pairs)
設計ノート
Solder the exposed thermal pad (EP) of the LTC2294CUP to a continuous ground pour on the top layer and stitch it with at least 9 thermal vias (0.3 mm drill) to the inner ground plane. Place AVDD bypass capacitors (0.1uF ceramic in parallel with 10uF tantalum) within 2 mm of every AVDD pin. Per LTC2294 datasheet 2294fa PCB layout section, routing the analog inputs as a 100 ohm differential microstrip with 2W spacing minimizes reflections and preserves the 90 dB SFDR.
Drive the LTC2294CUP analog inputs with a low-impedance differential buffer (AD8138 or AD8352). Single-ended drive reduces SNR by 6 dB and degrades SFDR by 8-12 dB. Maintain 50 ohm transmission-line impedance from the buffer output to the AIN pins using controlled-impedance traces. Use an aperture delay-matched clock source (e.g., AD9520) to keep ENC edge-to-ENC phase noise below 0.5 ps RMS; this is essential to hit the rated 70.6 dB SNR at full input frequency.
Do not leave the OF (output format) pin floating - tie it to OVDD for offset-binary mode or to OGND for two's complement. Failing to do this causes the digital outputs to enter an invalid state at power-up. Also, decouple the REFT1/REFB1 and REFT2/REFB2 reference pins individually - sharing a single bypass cap between channels can couple switching noise from channel 1 into channel 2 and break the 110 dB isolation spec.
Estimated: at 422 mW total dissipation in a 64-pin QFN 9x9 mm with the EP soldered to a 4-layer FR4 board (typical theta_JA around 30 C/W per JEDEC EIA/JESD51), the junction temperature rise above ambient is approximately 13C. Within the 0C to +70C commercial range this is comfortable, but in sealed enclosures without airflow the ambient should be kept below 57C to stay within spec.
コンプライアンス情報
RoHS compliance indicated by #PBF suffix per Linear Technology/Analog Devices convention. C-grade part (0C to +70C) is not AEC-Q100 qualified; choose LTC2294IUP for industrial temperature or contact Analog Devices for automotive-grade options.
