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EPM9320ALC84-10N - 320-Macrocell MAX 9000 CPLD, 10ns, 84-PLCC
EPM9320ALC84-10N

EPM9320ALC84-10N - 320-Macrocell MAX 9000 CPLD, 10ns, 84-PLCC

The Intel (formerly Altera) EPM9320ALC84-10N is a 320-macrocell, 6,000-gate CMOS Complex Programmable Logic Device (CPLD) from the MAX 9000 family, housed in an 84-pin Plastic Leaded Chip Carrier (PLCC) package. The -10 speed grade corresponds to a 10 ns pin-to-pin delay, and the device supports an internal toggle frequency up to 144.9 MHz at 5 V operation. The MAX 9000A family combines high density, in-system programmability, and predictable interconnect timing for glue-logic, bus-interface, and state-machine consolidation designs. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that sits hierarchically between simple PAL/GAL splds and high-density FPGAs. It provides predictable timing, instant-on operation, and high fan-in macrocell structures, making it ideal for deterministic control logic. CPLDs are typically used for address decoding, peripheral interfacing, bus bridging, and power-sequencing controllers where fixed, low-latency response is required. The MAX 9000 family extends classic EPLD architecture to higher logic densities while retaining the deterministic timing that made the MAX 5000 and MAX 7000 families popular in telecom, industrial, and embedded designs. Key features of the EPM9320ALC84-10N include 320 macrocells distributed across 16 logic array blocks (LABs), 60 user I/O pins, 5 V core operation (5.0 V nominal VCC), in-system programmability via JTAG (IEEE 1149.1), and a commercial 0C to 70C operating temperature range. The device includes per-macrocell registers, programmable interconnect array (PIA), and dedicated input/output control blocks. The 84-pin PLCC package provides through-hole compatibility for legacy industrial backplanes, retrofit designs, and existing production assemblies where socket replacement is preferable to redesign. From an architectural standpoint, the EPM9320A uses Altera's classic MAX architecture with EEPROM-based configuration cells, meaning the device retains its programmed logic without external boot memory. Configuration is loaded via JTAG using a ByteBlaster or compatible programmer, and the part can be reprogrammed thousands of times. The 10 ns tPD and 144.9 MHz fCNT make this part suitable for state machines running at moderate clock rates and for pipelined control logic. Typical applications include legacy industrial control boards, telecom line-card glue logic, address-decoding and chip-select generation, peripheral bus interfacing (ISA, PCI, VME), motor-control state machines, and retrofit/repair scenarios where the original MAX 9000 part must be replaced. The part is also widely used in educational boards, prototype development, and military/aerospace systems where the MAX 9000 family has long design-cycle approval. When designing with the EPM9320ALC84-10N, observe the recommended 5.0 V VCC tolerance (the A-suffix denotes 5 V operation, not the 3.3 V-compatible LC/RC/QI variants). Decouple each VCC/ground pair with a 0.1 F ceramic capacitor placed within 50 mils of the package pin, and adhere to the JTAG chain layout guidelines for multi-device boundary-scan configurations. The 84-PLCC socket should be a low-profile machine-pin or open-frame type rated for the operating temperature range. This page synthesizes distributor pricing, drop-in alternatives drawn from the same MAX 9000 family, and practical design notes not found in the manufacturer datasheet alone.

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EPM9320ALC84-15 - MAX 9000 CPLD, 320 Macrocells, 16ns, 84-PLCC | Altera
EPM9320ALC84-15

EPM9320ALC84-15 - MAX 9000 CPLD, 320 Macrocells, 16ns, 84-PLCC | Altera

The Altera EPM9320ALC84-15 is a member of the MAX 9000 Complex Programmable Logic Device (CPLD) family, delivering 320 macrocells organized in 16 logic array blocks (LABs), 56 usable I/O pins, and a 16 ns worst-case propagation delay in a 84-pin Plastic Leaded Chip Carrier (PLCC, J-lead) package with the package designator S-PQCC-J84. The device is fabricated on a 5 V CMOS process and is intended for high-density glue-logic, bus-interface, and state-machine integration in 5 V-tolerant industrial, telecom, and embedded systems. A CPLD (Complex Programmable Logic Device) is a non-volatile, instantly-on programmable logic device that combines multiple PAL-like macrocell blocks with a central interconnect matrix. The MAX 9000 family sits between classic 22V10-style SPLDs and larger FPGAs, targeting designs that need deterministic timing, ISP (in-system programmability) via JTAG, and 100% route-ability at densities up to ~560 macrocells. Compared with an FPGA, a CPLD such as the EPM9320ALC84-15 has lower absolute logic capacity but offers predictable pin-to-pin delays, no external boot PROM, and very low standby current. Key specifications include 320 macrocells, 6 K usable gates, a tPD of 16 ns, a 5 V ±5% (4.75 V to 5.25 V) supply, 56 user I/O lines, and 84 PLCC J-leads. The device supports IEEE Std 1149.1 JTAG boundary-scan, in-system programming via the JTAG port, and a power-down feature that minimizes standby consumption. The 84-pin PLCC package is through-hole-friendly and easy to hand-prototype, which is one of the reasons this part remains specified in long-lifecycle industrial controllers. Architecturally, the EPM9320ALC84-15 uses Altera's classic MAX architecture with EEPROM-based configuration cells, a programmable AND array feeding a fixed OR array, and per-macrocell flip-flops with programmable polarity. The interconnect is a continuous, fast-path switch matrix that delivers uniform 16 ns delays across all pins regardless of placement, which is the principal reason designers choose this family over look-alike FPGAs for control-plane logic. Typical applications include 5 V industrial PLC glue logic, ISA/PCI bus address decoding, motor-control state machines, telecom backplane control, and legacy ASIC replacement in medical and aerospace systems. Designers should also evaluate the EPM9320ALC84-10 (10 ns tPD) when margin is tight, or migrate to MAX II or MAX V CPLDs if lower power is required. When designing with the EPM9320ALC84-15, pay particular attention to the global clock and clear pin assignments and ensure that the JTAG chain is correctly ordered in multi-device boards. The device requires a single 5 V supply and supports ISP via JTAG; an external configuration PROM is not required. This page synthesizes distributor pricing for the EPM9320ALC84-15, same-package drop-in alternatives within the MAX 9000 family and from competing CPLD vendors, and practical design notes not consolidated in any single manufacturer document.

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EPM9320ALC84-20 - MAX 9000 EPLD, 84-PLCC, 20ns | Altera
EPM9320ALC84-20

EPM9320ALC84-20 - MAX 9000 EPLD, 84-PLCC, 20ns | Altera

The Altera EPM9320ALC84-20 is a member of the MAX 9000 family of high-density, high-performance Complex Programmable Logic Devices (CPLDs) housed in an 84-pin Plastic Leaded Chip Carrier (PLCC) package. This variant is specified for a 20 ns maximum pin-to-pin propagation delay (tPD) and is part of the mature Altera (now Intel) MAX CPLD portfolio targeting glue-logic integration, bus interfacing, and state-machine consolidation in legacy and industrial systems. The MAX 9000 family delivers 320 to 560 macrocells across multiple device options, fabricated on a 0.5 µm CMOS EEPROM process. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that sits between simple SPLDs/GALs and high-density FPGAs in the programmable logic hierarchy. CPLDs use a classic AND/OR PLA-style architecture with non-volatile EEPROM or flash configuration cells, providing instant-on operation at power-up with no external boot memory. In the broader taxonomy, the EPM9320 belongs to: CPLD -> programmable logic -> logic IC -> semiconductor device, and is positioned as the high-density endpoint of the Altera MAX legacy families that preceded the modern MAX II, MAX V, and MAX 10 device series. Key features of the EPM9320ALC84-20 include 320 macrocells, 16 logic array blocks (LABs), 212 user I/O pins, and a worst-case commercial-grade tPD of 20 ns through the Logic Array Blocks and Programmable Interconnect Array (PIA). The device supports 5.0 V in-system programmability via the IEEE 1149.1 JTAG interface and includes built-in JTAG boundary-scan test circuitry. The PLCC-84 package offers a JEDEC-standard 84-pin ceramic/leaded footprint with a 1.27 mm pitch. Architecturally, the EPM9320 employs the classic MAX 9000 multi-LAB structure, where each LAB contains 16 macrocells with configurable flip-flops, expanders, and product-term allocation. The Programmable Interconnect Array (PIA) provides deterministic, predictable routing with no contention, making the device well suited for asynchronous and clocked state-machine designs requiring fixed timing. Typical applications include legacy telecommunications backplane glue logic, industrial PLC I/O expansion and protocol bridging, military/aerospace systems requiring instant-on programmable logic, and drop-in replacement of multiple 74LS/74F discrete logic packages. The instant-on, non-volatile nature of MAX 9000 makes it especially attractive in deterministic boot scenarios where FPGAs would require an external configuration ROM. When designing with the EPM9320ALC84-20, verify that your tool flow targets the legacy MAX+PLUS II or Quartus II (legacy device support) software chain. Programming files are generated as .pof or .sof files, and the device uses 5V-tolerant I/O in commercial-grade variants. This page synthesizes distributor stock data, drop-in replacement candidates, and practical design notes for the mature MAX 9000 family - information not aggregated on any single manufacturer or distributor page.

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EPM9320ALI84-10 - MAX 9000 CPLD, 320 Macrocells, 84-PLCC | Intel
EPM9320ALI84-10

EPM9320ALI84-10 - MAX 9000 CPLD, 320 Macrocells, 84-PLCC | Intel

The Intel (formerly Altera) EPM9320ALI84-10 is a high-performance CMOS EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 9000 family, fabricated on an advanced CMOS technology. The device provides 6,000 to 12,000 usable gates, pin-to-pin delays as fast as 10 ns, and counter speeds of up to 144 MHz, all housed in an 84-pin PLCC package. It delivers 320 macrocells and is supported by 5.0-V in-system programmability (ISP) through a built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface. A Complex Programmable Logic Device (CPLD) is a non-volatile programmable logic device that combines multiple PAL/GAL-like macrocell blocks on a single die with a programmable interconnect matrix, sitting hierarchically between simple SPLDs/CPLDs and FPGAs in the programmable logic taxonomy: SPLD < CPLD < FPGA < programmable logic < semiconductor. The MAX architecture specifically uses a Multiple Array MatriX (MAX) interconnect that delivers predictable timing, a critical advantage over SRAM-based FPGAs for glue-logic and bus-interface roles where deterministic propagation delay matters. Key specifications of the EPM9320ALI84-10 include 320 macrocells, 84 user I/O pins, 10 ns pin-to-pin combinatorial delay (Tpd1), 144 MHz maximum counter frequency, and 5.0V VCC operation. The device also features four dedicated inputs, JTAG boundary-scan test compliance per IEEE 1149.1, and an industrial operating temperature range of -40C to +85C suitable for harsh environments. Architecturally, the MAX 9000 family integrates PAL-like logic array blocks (LABs) with a high-speed programmable interconnect array (PIA). The EEPROM process technology provides non-volatile configuration that retains the design pattern through power cycles without an external boot PROM, simplifying board design and reducing bill-of-materials cost. Typical applications include high-speed bus interfacing and address decoding in embedded systems, peripheral glue logic in telecommunications equipment, industrial control system logic integration, and replacement of multiple discrete 22V10/PAL/GAL devices in legacy board designs. The deterministic timing also makes it suitable for state-machine controller and protocol-bridge implementations. When designing with this part, note that -10 grade denotes 10 ns tpd; slower (-15, -20) and faster (-7) grades are available as pin-compatible drop-in replacements within the same 84-PLCC footprint. ISP via JTAG requires a 5V-tolerant TCK/TMS/TDI/TDO chain wired to a programming header or boundary-scan controller. This page synthesizes distributor pricing, drop-in same-family alternatives, JTAG programming guidance, and thermal/PCB layout notes that are not consolidated in the manufacturer datasheet alone.

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EPM9320ALI84-10N - 320-Macrocell 10ns MAX 9000 CPLD | Altera
EPM9320ALI84-10N

EPM9320ALI84-10N - 320-Macrocell 10ns MAX 9000 CPLD | Altera

The Altera EPM9320ALI84-10N is a high-density, in-system-programmable Complex Programmable Logic Device (CPLD) from the MAX 9000 family, delivering 320 macrocells, 20 Logic Array Blocks (LABs), and 6,000 to 12,000 usable gates in a 5.0-V CMOS EEPROM-based architecture. Housed in an 84-pin PLCC (Plastic Leaded Chip Carrier) package with J-bend terminals on a 1.270 mm pitch, this device offers pin-to-pin delays as fast as 10 ns and counter speeds up to 144 MHz, making it suitable for high-performance glue-logic, bus-interface, and state-machine applications. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL-like macrocells with a central interconnect matrix. In the system hierarchy, the CPLD sits between simple SPLDs (PAL/GAL) and FPGAs: it offers deterministic 10 ns timing, instant-on EEPROM configuration, and high I/O count, but lacks the fine-grained LUT fabric of an FPGA. The MAX 9000 family implements Altera's third-generation Multiple Array MatriX (MAX) architecture, which groups macrocells into LABs joined by a programmable interconnect array (PIA), enabling predictable timing and efficient state-machine implementation. Key features of the EPM9320ALI84-10N include 56 user I/O pins, separate VCCINT (5.0 V) and VCCIO pins for output-driver voltage selection (3.3 V or 5.0 V), and built-in IEEE Std. 1149.1 JTAG interface for in-system programmability (ISP). The device supports TTL-compatible inputs at 5.0-V VCCINT and offers multi-voltage I/O for mixed-voltage designs. Programmable power reduction modes lower quiescent current during standby, while the -10 speed grade delivers the fastest pin-to-pin delay in the MAX 9320 die family. The MAX architecture uses EEPROM configuration memory, which provides non-volatile storage and infinite re-programmability without external boot devices. The 320 macrocells are split into 20 LABs of 16 macrocells each, with each macrocell containing a programmable AND/OR array, a flip-flop, and configurable I/O control. This organization is optimized for wide combinatorial and registered logic functions typical of address decoding, bus arbitration, and asynchronous state-machine designs. Typical applications include high-performance bus-interface and address decoding in microprocessor systems, peripheral glue logic in telecom and networking equipment, industrial control and instrumentation logic, and replacement of multiple discrete TTL/CMOS MSI parts on legacy PCBs. The 84-pin PLCC package and through-hole-compatible socket footprint also make the EPM9320ALI84-10N a common choice for legacy industrial and military designs that require hand-reworkability. When designing with the EPM9320ALI84-10N, ensure that VCCINT is always tied to 5.0 V, while VCCIO can be set to 3.3 V or 5.0 V depending on the I/O rail. Use the JTAG interface for in-system re-programmability and boundary-scan testing, and observe the maximum I/O current ratings per bank to avoid output-buffer overheating. The -10 speed grade has the highest dynamic ICC; for lower-power designs, consider the slower -12 or -15 grades in the same MAX 9320 die family. This page synthesizes the manufacturer datasheet, current distributor stock levels, drop-in alternatives drawn from the same MAX 9000 family and competitor CPLD lines, and practical PCB design guidance not found in a single manufacturer document - information gain targeted at engineers maintaining or upgrading legacy 5 V MAX 9000 designs.

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EPM9320AR1208-10 - MAX 9000 EPLD, 1208-Pin PGA, 10ns | Intel / Altera
EPM9320AR1208-10

EPM9320AR1208-10 - MAX 9000 EPLD, 1208-Pin PGA, 10ns | Intel / Altera

The Intel / Altera (formerly Altera Corporation) EPM9320AR1208-10 is a member of the MAX 9000 Programmable Logic Device Family, a high-density, in-system programmable Erasable Programmable Logic Device (EPLD) fabricated in 0.7 µm CMOS EEPROM technology. The MAX 9000 family combines the look-up-table (LUT) architecture used in FPGAs with the macrocell architecture of classic EPLDs, yielding a logic density of 6,000 usable gates in the base device, packaged here in a 1208-pin ceramic/ceramic-equivalent Pin Grid Array (PGA) denoted by package code 'AR1208'. The speed grade '-10' designates a 10 ns pin-to-pin logic delay through the Logic Array Blocks (LABs) and Interconnect, supporting system clocks up to approximately 100 MHz in pipelined designs. A Programmable Logic Device (PLD) is a generic term that historically encompassed simple PAL/GAL devices, complex EPLDs like the MAX 9000 family, and modern FPGAs. The MAX 9000 sits in the middle of this hierarchy as a 'Complex PLD' (CPLD) - large enough to replace dozens of 7400-series SSI/MSI parts, small enough to retain the non-volatility, deterministic timing, and instant-on characteristics of classic PLDs. Within the broader taxonomy: programmable logic device -> EPLD -> complex EPLD (CPLD) -> MAX family -> MAX 9000 series. Key architectural features of the EPM9320AR1208-10 include multiple Logic Array Blocks interconnected by the Programmable Interconnect Array (PIA), a global routing structure that delivers predictable timing with fixed propagation delays. The 'A' suffix indicates the ceramic PGA package variant; the 'R' suffix indicates the device is supplied in tape-and-reel orientation suitable for legacy through-hole assembly flows. The device supports in-system programmability via the IEEE 1149.1 (JTAG) boundary-scan chain, allowing configuration updates without removing the part from the board, and offers JTAG-based read-back of device state for production test. Typical applications for the EPM9320AR1208-10 include legacy telecom interface glue logic, industrial control state machines, bus-address decoding, peripheral integration in VMEbus and Multibus II systems, and pin-compatible drop-in replacement of older discrete TTL/CMOS logic arrays. The MAX 9000 family is widely cited in applications notes for replacing 7400-series glue logic, custom state machines, and address decoders in long-lifecycle defense, aerospace, and industrial systems. When designing with this part, engineers should note that the MAX 9000 family has been in production since the mid-1990s and is approaching end-of-life; second-source qualification and last-time-buy planning are recommended. Programming is performed via the Altera ByteBlaster or compatible JTAG programmer using MAX+PLUS II or Quartus II development software. Surface-mount and lead-free variants exist in the MAX 7000 and MAX V families for new designs. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet alone.

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EPM9320ARC208-10 - MAX 9000 CPLD, 320 Macro, 10ns | Altera
EPM9320ARC208-10

EPM9320ARC208-10 - MAX 9000 CPLD, 320 Macro, 10ns | Altera

The Altera EPM9320ARC208-10 is a high-performance CMOS EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 9000 device family, delivering 320 macrocells with a 10 ns pin-to-pin logic delay in a 208-pin RQFP (Power Quad Flat Pack) package. The device integrates 6,000 usable gates and operates from a 5 V supply, offering 144.9 MHz maximum internal performance and in-system programmability (ISP) through the built-in IEEE Std. 1149.1 JTAG interface. The MAX 9000 architecture combines third-generation Multiple Array MatriX (MAX) technology with EEPROM configuration memory for instant-on, non-volatile behavior. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL/GAL-style macrocell arrays on a single chip with a global interconnect fabric. CPLDs sit in the broader taxonomy: programmable logic -> CPLD/FPGA family -> non-volatile logic. They are valued for deterministic, predictable timing (no configuration load latency), high I/O count, and instant-on operation, making them complementary to SRAM-based FPGAs in glue-logic, bus-interface, and power-up sequencing roles. Key features of the EPM9320ARC208-10 include programmable speed/power optimization (each macrocell can run at 50% or less power with only a nominal timing delay), JTAG-based IEEE 1149.1 boundary-scan test support, multi-voltage I/O compatibility, and built-in thermal management for the high-density RQFP package. The MAX 9000 family supports a wide range of package options including PLCC, RQFP, PGA, and BGA, all pin-compatible within a given package class for design flexibility. The device is fabricated on a 5.0 V CMOS EEPROM process, providing non-volatile storage of the logic configuration. The 320-macrocell array with 16 LABs (Logic Array Blocks) provides predictable, deterministic timing suitable for state machines, address decoding, and synchronous control logic. Typical applications include high-speed bus interface bridging, address decoding and chip-select generation, glue logic replacement for ASIC designs, industrial control systems, telecommunications infrastructure, and legacy system upgrades. The 5V tolerance makes it especially useful in industrial and telecom systems still based on 5V logic. When designing with the EPM9320ARC208-10, perform a complete thermal analysis as recommended in Altera Application Note 74 (Evaluating Power for Altera Devices) before committing the design. The RQFP-208 package's power dissipation capability depends significantly on PCB layout, copper area, and airflow, so adequate thermal relief is essential for reliable high-speed operation. This page synthesizes distributor stock status, drop-in MAX 9000 alternatives, and practical design notes not consolidated in any single manufacturer datasheet.

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EPM9320ARC208-10N - 320-Macrocell MAX 9000 CPLD, 10ns | Altera
EPM9320ARC208-10N

EPM9320ARC208-10N - 320-Macrocell MAX 9000 CPLD, 10ns | Altera

The Altera EPM9320ARC208-10N is a 320-macrocell, 6,000-gate CMOS Complex Programmable Logic Device (CPLD) from the MAX 9000 family, packaged in a 208-pin RQFP (Plastic Quad Flat Pack) with exposed pad. It provides 10 ns pin-to-pin logic delay, 144.9 MHz maximum operating frequency, and operates from a 5 V supply, integrating high-density system-level logic in a single non-volatile device. What is a CPLD? A Complex Programmable Logic Device (CPLD) is a non-volatile programmable logic IC that combines multiple PAL/GAL-style macrocell arrays with a central programmable interconnect matrix. In the broader taxonomy, a CPLD sits between simple SPLDs (PALs, GALs, 22V10s) and FPGAs: CPLDs offer deterministic timing, instant-on non-volatile configuration (EEPROM-based in MAX 9000), predictable I/O pin-to-pin delays, and high drive strength, while FPGAs provide higher logic density and richer register features at the cost of volatile configuration and longer propagation delays. CPLDs are typically chosen for glue logic, bus interface bridging, state-machine controllers, and power-up instant-on decoding. Key features of the EPM9320ARC208-10N include 320 macrocells distributed across 16 Logic Array Blocks (LABs), 12 dedicated input pins, and 168 user I/O pins. It supports in-system programmability via IEEE Std. 1149.1 JTAG, includes an open-drain JTAG pin option, and provides 5 V tolerant I/O. The 'ARC' suffix indicates the 208-pin RQFP package; the '10' speed grade gives the 10 ns tPD timing; and the trailing 'N' indicates a lead-free / RoHS-compliant finish. Architecturally, the MAX 9000 device uses an enhanced EPLD architecture with multiple LABs interconnected by the Programmable Interconnect Array (PIA). Each LAB contains 16 macrocells, each with a programmable AND/OR array, configurable flip-flop, and I/O architecture. The non-volatile EEPROM configuration cell provides instant-on behavior at power-up with no external configuration PROM required, distinguishing MAX 9000 from SRAM-based FPGAs and giving it deterministic boot for critical control paths. Typical applications include high-speed bus decoding and address mapping, peripheral interfacing and glue logic in microprocessor systems, state-machine control, fast datapath multiplexing, JTAG-driven board-level test integration, and legacy 5 V system logic consolidation. Designers select this part when they need fast deterministic pin-to-pin delays combined with non-volatile instant-on configuration. When designing with the EPM9320ARC208-10N, ensure VCC rises monotonically during power-up, place decoupling capacitors (0.1 uF plus bulk) close to every VCC pin, and respect the input undershoot/overshoot limits (transitions may undershoot to -2.0 V or overshoot to 7.0 V only for periods under 20 ns at no-load). Use the JTAG chain to program in-system; the open-drain JTAG pin requires an external pull-up. This page consolidates distributor pricing, same-package drop-in speed-grade variants, and design notes not found in the original datasheet.

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EPM9320ARI208-10 - MAX 9000 CPLD 320 Macrocell | Intel
EPM9320ARI208-10

EPM9320ARI208-10 - MAX 9000 CPLD 320 Macrocell | Intel

The Intel (Altera) EPM9320ARI208-10 is a MAX 9000 family Complex Programmable Logic Device (CPLD) offering 320 macrocells, 6,000 usable gates, and 132 user I/O pins, with a 10 ns pin-to-pin propagation delay and counter frequencies up to 144.9 MHz, housed in a 208-pin RQFP (BFQFP) package with exposed pad. It operates from a 4.5 V to 5.5 V supply and is rated for the industrial temperature range of -40 C to +85 C. A CPLD (Complex Programmable Logic Device) is a programmable logic IC that combines multiple logic blocks, macrocells, and a programmable interconnect array on a single die, allowing designers to implement custom digital logic without fabricating an ASIC. Within the broader taxonomy, the EPM9320 belongs to the CPLD class, which sits under programmable logic devices (PLDs), which in turn fall under digital logic ICs and integrated circuits. CPLDs are distinguished from FPGAs by their non-volatile configuration memory and deterministic, single-cycle timing. The EPM9320ARI208-10 is built on Altera's third-generation Multiple Array MatriX (MAX) architecture using high-performance CMOS EEPROM technology. Its 320 macrocells are organized into 20 logic array blocks (LABs), each containing 16 macrocells with a dual-output structure that permits independent use of combinatorial and registered logic. The EEPROM-based configuration is non-volatile, meaning the device retains its programmed logic at power-up without an external configuration PROM, unlike SRAM-based FPGAs. Key performance attributes include 10 ns pin-to-pin logic delays, counter frequencies up to 144.9 MHz, and full compliance with the PCI Local Bus Specification Revision 2.2 as defined by the PCI Special Interest Group (PCI SIG). The device supports 5.0 V in-system programmability (ISP) through a built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface, enabling boundary-scan testing and field reprogramming. Typical applications include PCI bus interface logic, glue logic consolidation, address decoding, state machines, and bus bridging in industrial control, telecommunications, and legacy computing platforms. The 132 I/O pins and 208-pin RQFP footprint suit designs requiring wide parallel buses. When designing with this device, note that it is a 5 V core part; level shifting is required when interfacing with 3.3 V or lower logic. The exposed-pad RQFP package requires a thermal land on the PCB for adequate heat dissipation. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet, providing engineers with a single reference for replacement and sourcing decisions.

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EPM9320ARI208-10N - MAX 9000 CPLD, 320 Macrocells, 208-RQFP | Altera
EPM9320ARI208-10N

EPM9320ARI208-10N - MAX 9000 CPLD, 320 Macrocells, 208-RQFP | Altera

The Altera EPM9320ARI208-10N is a high-density CMOS EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 9000 device family, featuring 6,000 usable gates, 320 macrocells, and a maximum operating frequency of 144.9 MHz in a 208-pin RQFP (industrial temperature grade) package. Built on Altera's third-generation Multiple Array MatriX (MAX) architecture, this device delivers 10 ns pin-to-pin logic delay (the "-10" speed grade), making it suitable for high-performance glue-logic, bus interfacing, and state-machine control applications. A CPLD (Complex Programmable Logic Device) is a non-volatile, flash/EEPROM-backed programmable logic device that combines the architectural simplicity of PAL/GAL with the density of an FPGA. In the system hierarchy, CPLDs sit between simple PLDs (PAL/GAL/22V10) and FPGAs - they offer instant-on configuration, deterministic timing, and high pin-count flexibility, making them ideal for interface bridging, power-sequencing logic, and address decoding on printed circuit boards. Key specifications of the EPM9320ARI208-10N include 4.5V to 5.5V single-supply operation, 20 Logic Array Blocks (LABs), 16 dedicated input pins for global signals, IEEE Std. 1149.1 JTAG interface for 5.0-V in-system programmability (ISP), and an industrial operating temperature range of -40C to +85C. The 208-pin RQFP (also called R-FQFP, plastic QFP with exposed pad for thermal dissipation) package supports surface-mount assembly with high board-density pinout. The MAX 9000 architecture integrates a programmable interconnect array (PIA) that routes signals between LABs and I/O pins with predictable, deterministic timing - this is critical for replacing discrete TTL/CMOS glue logic on legacy boards. Each macrocell contains a programmable AND/OR array with a flip-flop, supporting registered, combinational, and tri-state output configurations. Typical applications include industrial automation controllers, telecommunications infrastructure (legacy line cards, bus arbiters), military and aerospace systems requiring 5V-tolerant logic, address decoding and chip-select generation for microprocessors, and PCI-to-ISA bus bridging designs. The -10 speed grade (10 ns tPD) is the standard speed bin, balancing timing margin against power consumption. When designing with this device, verify that the 208-RQFP footprint is compatible with your PCB layout and confirm availability of the Altera MAX+PLUS II or Quartus design toolchain (legacy support) for programming. Note that the MAX 9000 family was discontinued per Altera PDN0711 in 2008 - this part is now supported only through the secondary market. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet.

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EPM9320BC356-15 - MAX 9000 CPLD, 320 Macro, 15ns, BGA-356 | Altera
EPM9320BC356-15

EPM9320BC356-15 - MAX 9000 CPLD, 320 Macro, 15ns, BGA-356 | Altera

The Altera EPM9320BC356-15 is a high-performance CMOS EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 9000 device family, built on the third-generation Multiple Array MatriX (MAX) architecture. It integrates 320 macrocells with a 15 ns pin-to-pin propagation delay and is housed in a 356-ball LBGA (BGA-356) package rated for the commercial temperature range. The device supports 5.0-V in-system programmability (ISP) through the IEEE Std. 1149.1 JTAG interface, enabling board-level reconfiguration without removal. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL/GAL-like macrocell arrays with a programmable interconnect network. CPLDs sit in the programmable logic hierarchy above simple PLDs (SPLDs) and below FPGAs, offering deterministic timing, fast input-to-output response, and instant-on behavior. The MAX 9000 series is built on EEPROM process technology, retaining configuration without external memory and supporting thousands of erase/program cycles. This positions the MAX 9000 family between low-density SPLDs and SRAM-based FPGAs in the programmable logic taxonomy. Key features of the EPM9320BC356-15 include 320 macrocells, a 15 ns maximum pin-to-pin delay, 5.0-V VCC operation (4.75 V to 5.25 V), JTAG-ISP compliance per IEEE 1149.1, and high-density programmable logic in a 356-ball LBGA package. The MAX architecture provides predictable, deterministic timing suitable for control logic, bus interfacing, and glue-logic replacement. The third-generation MAX architecture implements a unified interconnect that routes signals across Logic Array Blocks (LABs) with consistent propagation delays, making static timing analysis straightforward. Built-in JTAG boundary-scan test circuitry supports IEEE 1149.1 testing, while the EEPROM-based configuration cells provide instant-on operation at power-up with no boot time and no external configuration memory required. Typical applications include high-speed glue logic, bus interfacing and protocol bridging, state-machine controllers, and address decoding in microprocessor and DSP systems. The MAX 9000 series is widely used in telecommunications equipment, industrial control systems, and legacy designs where deterministic timing and instant-on behavior are mandatory. When designing with the EPM9320BC356-15, ensure 5.0-V tolerance on all I/O signals and respect the commercial temperature grade. Use the Altera MAX+PLUS II or Quartus design tools for development. Note that the MAX 9000 family is mature, and lifecycle status should be verified with distributors before committing to new designs. This page synthesizes distributor pricing, MAX 9000 family drop-in alternatives, and practical design notes not found in a single manufacturer datasheet or distributor catalog page.

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EPM9320GC280-15 - 320-Macrocell MAX 9000 CPLD, 15ns, CPGA-280 | Altera
EPM9320GC280-15

EPM9320GC280-15 - 320-Macrocell MAX 9000 CPLD, 15ns, CPGA-280 | Altera

The Altera EPM9320GC280-15 is a 320-macrocell member of the MAX 9000 family of high-performance CMOS EEPROM-based programmable logic devices (PLDs) built on the third-generation Multiple Array MatriX (MAX) architecture. Housed in a 280-pin ceramic pin-grid array (CPGA) package, the device provides 6,000 usable gates, a 16 ns pin-to-pin propagation delay (the -15 speed grade), and a maximum internal clock frequency of 117.6 MHz. It operates from a 4.75 V to 5.25 V single supply and supports 3.3 V or 5 V configurable I/O on up to 164 user I/O pins. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device containing multiple PAL-like logic array blocks (LABs) interconnected by a programmable switch matrix; it sits between discrete PALs and FPGAs in the programmable-logic taxonomy. The MAX architecture places each macrocell between a logic array and an I/O pin, giving deterministic, predictable timing that is independent of internal routing - a property that distinguishes CPLDs from SRAM-based FPGAs and makes the MAX 9000 family well suited to control-plane and glue-logic applications. Key features include 5.0-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 JTAG interface, programmable macrocell flip-flops with individual clear/preset, four pin feedback paths per I/O, and a JTAG Instruction Register supporting BYPASS, EXTEST, SAMPLE/PRELOAD, IDCODE, and USERCODE. The on-chip EEPROM cells provide zero-power standby (typically <100 mA quiescent) and instant-on operation without external boot devices. Typical applications span high-density bus decoding, peripheral control, and state-machine replacement in industrial, telecom, and embedded systems where deterministic timing and non-volatility are required. Designers frequently pair the EPM9320 with SRAM, DRAM, and Flash controllers, bus bridges, and glue logic between microprocessors and peripherals. When designing with the EPM9320GC280-15, allocate sufficient decoupling (100 nF + 10 uF near each supply pin) and route JTAG TMS/TCK/TDI/TDO with short traces to maintain ISP margin. Because the CPGA-280 package is socket-friendly but not reflow-compatible, plan board assembly around a PGA socket for rework flexibility. This page consolidates distributor stock and pricing, drop-in alternatives sharing the CPGA-280 footprint, and applied design guidance not found in the original Altera datasheet alone, giving procurement and engineering teams a single source for EPM9320GC280-15 information.

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EPM9320GC280-20 - MAX 9000 CPLD, 320 Macrocells, 280-CPGA | Altera
EPM9320GC280-20

EPM9320GC280-20 - MAX 9000 CPLD, 320 Macrocells, 280-CPGA | Altera

The Altera EPM9320GC280-20 is a high-performance CMOS EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 9000 device family, featuring 320 macrocells, approximately 6,000 usable gates, and a 100 MHz internal frequency. It is housed in a 280-pin Ceramic Pin Grid Array (CPGA) package and supports 5.0-V in-system programmability (ISP) through a built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL/GAL-like macrocell blocks on a single chip with a programmable interconnect matrix. Positioned in the programmable logic hierarchy between small SPLDs and large FPGAs, CPLDs are widely used for glue logic, bus interfacing, state machines, and boot-time control functions where deterministic propagation delay and instant-on configuration are required. The MAX 9000 family represents Altera's third-generation Multiple Array MatriX (MAX) architecture, which delivers higher density and faster performance than earlier MAX families. Key features of the EPM9320GC280-20 include 320 macrocells across multiple Logic Array Blocks (LABs), a maximum propagation delay of approximately 23 ns (tpd1), a 100 MHz internal counter frequency, and 5.0-V VCC operation. The device offers built-in JTAG boundary-scan support compliant with IEEE 1149.1, 5.0-V in-system programmability, and pin counts up to 280 in ceramic PGA packaging for high-reliability applications. Architecturally, the MAX 9000 uses a MultiCore architecture with each macrocell containing a programmable AND/OR array, a flip-flop, and configurable I/O. The non-volatile EEPROM configuration memory provides instant-on behavior at power-up with no external boot PROM required, distinguishing the MAX family from SRAM-based FPGAs. This makes the EPM9320GC280-20 ideal for systems requiring deterministic, microsecond-scale startup. Typical applications include high-speed controller glue logic, address decoding and bus arbitration in microprocessor systems, telecommunications line-card interface logic, industrial automation controllers, and military/aerospace systems that benefit from the ceramic CPGA package's hermeticity and thermal performance. When designing with the EPM9320GC280-20, engineers should follow Altera's MAX 9000 datasheet recommendations for decoupling, JTAG chain ordering, and I/O bank grouping. The CPGA package requires a socket or through-hole PCB footprint with adequate thermal relief for high-reliability operating environments. This page synthesizes distributor pricing, same-family drop-in alternatives, and practical design notes not found in the original manufacturer datasheet, enabling faster component selection and BOM validation.

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EPM9320LC84-10 - MAX 9000 EPLD, 84-PLCC, 10ns | Intel / Altera
EPM9320LC84-10

EPM9320LC84-10 - MAX 9000 EPLD, 84-PLCC, 10ns | Intel / Altera

The Intel (formerly Altera) EPM9320LC84-10 is a member of the MAX 9000 Erasable Programmable Logic Device (EPLD) family, offering 320 macrocells (approximately 6,000 usable gates) of high-density programmable logic in an 84-pin plastic J-leaded chip carrier (PLCC) package with a 10 ns pin-to-pin logic delay (-10 speed grade). It is a non-volatile, UV-erasable CMOS EPLD intended for medium-complexity glue-logic, bus-interface, and state-machine integration where deterministic timing and instant-on behavior are required. What is an EPLD? An Erasable Programmable Logic Device is a type of programmable logic that sits between classic PAL/GAL devices and larger FPGAs in the programmable logic hierarchy (PAL/GAL -> CPLD/EPLD -> FPGA -> SoC FPGA). Unlike SRAM-based FPGAs, EPLDs use non-volatile EEPROM/UV-EPROM cells for configuration, so they power up instantly in a known state with no external boot PROM. The MAX 9000 family is built on a hierarchical, PLA-style architecture with multiple Logic Array Blocks (LABs) joined by a Programmable Interconnect Array (PIA), which gives MAX 9000 parts predictable, fixed-delay timing that is easier to budget than FPGA routing. The EPM9320LC84-10 provides 320 macrocells across 16 LABs, supports in-system programmability via the JTAG-compliant IEEE 1149.1 boundary-scan interface, and offers 5V-tolerant I/O on most members of the family. Its 10 ns combinatorial propagation delay and 134 MHz internal counter frequency make it suitable for high-speed control logic, address decoding, and bus arbitration in systems built around microprocessors, microcontrollers, or DSPs. The part is fabricated on a 0.7 µm CMOS EEPROM process, supplied in a 84-pin PLCC package (JEDEC outline MO-047), and is RoHS/RoHS3 compliant per the modern Intel material declaration. The pinout follows the standard MAX 9000 PLCC-84 assignment, and the device is supported by legacy Altera development tools (MAX+PLUS II and Quartus MAX device support). It is widely used in legacy industrial controllers, telecom line cards, test instruments, and aerospace systems where the design was qualified decades ago and the same part must be sourced for ongoing production or repair. Typical applications include 32-bit address decoding for embedded CPU boards, IEEE-1284 parallel-port peripherals, ISA/PCI bus interface glue logic, programmable keyboard/video/mouse controllers, and digital state machines in industrial PLCs. The instant-on non-volatile configuration means no boot time and no bitstream loader, which is a decisive advantage over SRAM FPGAs in deterministic boot-critical systems. When designing with this part, note that the EPM9320LC84-10 is a long-lifecycle legacy device. Most original Altera MAX 9000 variants have been migrated to lead-free or lead-bearing packages, and the part is sourced primarily through distributors holding legacy stock or through independent distributors. Always verify the date code and traceability documents before placing the part into a new design, and consider the modern MAX II / MAX V families for new designs unless pin/footprint compatibility with EPM9320LC84-10 is mandatory. This page synthesizes distributor pricing, exact same-package drop-in alternatives, comparison parameters, and practical legacy-sourcing notes not found in any single datasheet, so engineers and buyers can evaluate the EPM9320LC84-10 in seconds.

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EPM9320LC84-15 - MAX 9000 CPLD 320-Macrocell 84-PLCC | Intel
EPM9320LC84-15

EPM9320LC84-15 - MAX 9000 CPLD 320-Macrocell 84-PLCC | Intel

The Intel EPM9320LC84-15 is a high-performance CMOS EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 9000 family, delivering 320 macrocells and 6,000 usable gates in an 84-pin Plastic Leaded Chip Carrier (PLCC) package. It features a 15 ns maximum propagation delay (tPD) and operates from a 5.0 V supply (4.75 V to 5.25 V), supporting 5.0 V in-system programmability (ISP) through a built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface for boundary-scan test and on-board reconfiguration. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic IC that combines the instant-on characteristics of classic PAL/GAL architectures with the density of modern FPGAs. The MAX architecture organizes logic into Logic Array Blocks (LABs) interconnected by a programmable interconnect matrix, with each macrocell containing a product-term array, a programmable flip-flop, and configurable I/O steering - placing CPLDs in the hierarchy: macrocell -> LAB -> CPLD -> programmable logic -> semiconductor device. The EPM9320LC84-15 supports a maximum clock frequency of 117.6 MHz and provides up to 212 user I/O pins in the largest package of the family. Its pin-locking architecture ensures that any change to the user's logic design does not alter pin assignments, simplifying PCB layout and design migration. The device also supports JTAG-based IEEE 1149.1 boundary-scan testing and includes built-in pull-up resistors on every I/O for reliable tri-state bus interfacing. Typical applications include bus interface bridging (PCI-to-ISA, address decoding), peripheral glue logic, state-machine controllers, and high-performance control logic replacement for multiple SSI/MSI components. Designers commonly deploy the EPM9320LC84-15 in telecom backplane controllers, industrial automation I/O expanders, and legacy system upgrades where 5 V tolerant logic and deterministic 15 ns timing are required. When designing with this device, ensure VCC ramps monotonically between 4.75 V and 5.25 V per the operating requirements; undershoot below -0.5 V or overshoot above 7.0 V on I/O pins (under no-load conditions, for periods shorter than 20 ns) is permissible only during fast transitions. Decoupling with 0.1 microfarad and 10 microfarad capacitors adjacent to every VCC pin is recommended.

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EPM9320LC84-20 - MAX 9000 CPLD, 320 Macros, 84-PLCC | Altera
EPM9320LC84-20

EPM9320LC84-20 - MAX 9000 CPLD, 320 Macros, 84-PLCC | Altera

The Altera EPM9320LC84-20 is a high-performance CMOS EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 9000 family, packaged in an 84-pin Plastic Leaded Chip Carrier (PLCC) and offering 320 macrocells with 60 user I/O pins. It is built on Altera's third-generation Multiple Array MatriX (MAX) architecture, providing 16 ns pin-to-pin propagation delay and an internal counter frequency of up to 118 MHz (also referenced at 144 MHz in some vendor sources). The device operates from a single 5.0 V supply and supports in-system programmability (ISP) via the IEEE Std. 1149.1 JTAG interface. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL-like macrocell arrays on a single chip with a programmable interconnect network. CPLDs sit in the hierarchy between simple PLDs (PAL/GAL) and FPGAs, offering deterministic timing, instant-on configuration from on-chip EEPROM, and high pin-to-pin logic density. They are commonly used for glue logic, address decoding, bus interface bridging, and state machine implementation where predictable timing and zero-configuration-boot behavior are required. Key features of the EPM9320LC84-20 include four dedicated low-skew global input pins (typically used for clock, clear, and output enable), dual-output macrocells that allow independent use of combinatorial and registered logic, and PCI Local Bus Specification Revision 2.2 compliance for 33 MHz PCI designs. The 5.0 V core and I/O supply, combined with JTAG-based ISP, makes it well suited for legacy industrial backplanes and telecom infrastructure where 3.3 V-only FPGAs cannot be used. The MAX 9000 architecture divides the device into Logic Array Blocks (LABs) interconnected by the Programmable Interconnect Array (PIA). Each macrocell contains a programmable AND/OR array, a configurable flip-flop, and product-term allocation logic, allowing wide fan-in functions to be implemented efficiently. The EPM9320 derivative is the second-largest member of the family, providing approximately 12,000 usable gates. Typical applications include PCI bus interface controllers, peripheral address decoding in 5 V microprocessor systems, industrial control glue logic, telecom line-card control planes, and replacement of multiple discrete PAL/GAL devices. The 0 to 70 C commercial temperature range suits enclosed indoor equipment such as base stations, factory controllers, and test instrumentation. When designing with this part, observe the 5.0 V I/O requirement and ensure all driven signals are 5 V tolerant at the receiver. The 84-pin PLCC socket allows easy prototyping but consumes more board area than equivalent QFP packages; consider the EPM9320RC208 or EPM9320GC280 variants if board space is constrained. This page synthesizes distributor availability, parametric pricing as of 2026-09-13, MAX 9000 family drop-in alternatives, and practical design notes that are not duplicated on the manufacturer datasheet, helping engineers shorten sourcing and qualification cycles.

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EPM9320LC84-20N - 320-Cell MAX 9000 CPLD, 84-PLCC | Intel / Altera
EPM9320LC84-20N

EPM9320LC84-20N - 320-Cell MAX 9000 CPLD, 84-PLCC | Intel / Altera

The Intel / Altera EPM9320LC84-20N is a high-performance CMOS EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 9000 family, delivering 6,000 usable gates with 320 macrocells in an 84-pin Plastic Leaded Chip Carrier (PLCC) package. Operating from a 5 V supply with a propagation delay of 16 ns (tPD) and an internal frequency up to 118 MHz, this device targets glue-logic, bus-interface, and state-machine consolidation in industrial and commercial systems. According to the manufacturer datasheet, the -20 speed grade corresponds to a 16 ns pin-to-pin delay, placing this part in the standard-performance tier of the MAX 9000 lineup. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL-like logic blocks on a single chip with a centralized interconnect matrix. The MAX 9000 architecture represents Altera's third-generation Multiple Array MatriX (MAX) implementation, providing predictable timing, in-system programmability via IEEE 1149.1 JTAG, and 5.0-V in-system programmability (ISP). Within the broader taxonomy, the EPM9320LC84-20N belongs to: CPLD -> programmable logic device -> digital IC -> semiconductor. Key features include 60 user I/O pins, J-bend terminal form with a QCCJ (PLCC) package outline, commercial temperature grading (0C to +70C), and CMOS logic family operation. The device supports 5-V in-system programmability and is built on a 0.5um triple-layer-metal EEPROM process, allowing logic retention without external memory. The 84-pin PLCC package offers a square footprint with 60 usable I/Os plus dedicated programming, JTAG, and power pins. The MAX 9000 family uses a hierarchical interconnect structure that routes signals between Logic Array Blocks (LABs) and the Programmable Interconnect Array (PIA), delivering consistent timing regardless of design placement. This deterministic timing model is one of the primary reasons CPLDs continue to be selected over FPGAs for fixed-timing glue logic applications such as address decoding, interrupt control, and bus arbitration. Typical applications include address decoding and bus interface logic in legacy embedded systems, glue logic between microprocessors and peripherals, industrial control boards requiring deterministic timing, state-machine and sequencer implementation, replacement of discrete 74LS/74HC TTL glue, and 5-V tolerant I/O expansion for older MCU designs. The 5-V native I/O is a key reason engineers continue to specify MAX 9000 parts in mixed-voltage designs. When designing with this device, observe the 5-V VCC requirement and ensure all inputs do not exceed the absolute maximum ratings. Decouple VCC with 0.1uF and 10uF capacitors placed close to the PLCC pins, and use the JTAG port (TMS, TCK, TDI, TDO) for in-system programming. Note that the EPM9320LC84-20N is a mature, long-lived part still widely used for legacy industrial designs. This page synthesizes distributor pricing, drop-in speed-grade and package alternatives from the MAX 9000 family, and practical design notes not collected in the manufacturer datasheet.

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EPM9320LI84-20 - MAX 9000 CPLD, 320 Macro, 60 I/O | Altera
EPM9320LI84-20

EPM9320LI84-20 - MAX 9000 CPLD, 320 Macro, 60 I/O | Altera

The Altera (now Intel) EPM9320LI84-20 is a high-density CMOS EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 9000 family, packaged in an 84-pin PLCC with J-lead (plastic leaded chip carrier) and rated for the industrial temperature range. It integrates 320 macrocells and provides 60 user I/O pins, with a 20 ns pin-to-pin propagation delay, and is fabricated on the third-generation Multiple Array MatriX (MAX) architecture. The device operates from a 5.0 V supply and supports in-system programmability (ISP) via IEEE Std. 1149.1 JTAG, enabling fast design iteration and field upgrades. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL/GAL-like logic blocks on a single chip with a programmable interconnect matrix. Within the broader taxonomy, a CPLD sits between small PLDs (PALs, GALs) and FPGAs: it provides fast, deterministic propagation delay (typically 5-20 ns regardless of routing), non-volatile on-chip configuration, and high-drive I/O suitable for bus interfacing and glue-logic replacement. CPLDs are commonly used as address decoders, bus interface bridges, state machines, and configuration controllers in microprocessor and DSP systems. The MAX 9000 family specifically targets high-density glue-logic consolidation, replacing multiple discrete PALs with a single device. Key differentiating features of the EPM9320LI84-20 include its 320-macrocell capacity (the highest density in the MAX 9000 family), 60 user I/Os with 5-V tolerant I/O banks, and an internal operating frequency of up to 118 MHz. The 20 ns tPD is suitable for memory interface glue logic, peripheral controllers, and bus arbitration functions running at up to 50 MHz. The device supports the familiar Altera MAX+PLUS II and Quartus development flows and is pin-compatible with the MAX 9000 LC and GC speed/package variants in the same 84-PLCC pinout, simplifying second-source qualification and lifecycle migration planning. Typical applications include high-density address decoding for 32-bit and 64-bit microprocessor systems, peripheral bus interfacing (PCI, ISA, VME bridges), state-machine controllers for industrial automation, JTAG-based ISP configuration of downstream devices, and legacy logic consolidation where a board was originally implemented with multiple 22V10 or 32-macrocell PALs. The non-volatile EEPROM configuration means the device powers up in a known state without an external boot PROM, simplifying system bring-up. When designing with this part, note that the -20 speed grade is the slowest in the MAX 9000 family; for higher throughput, designers should consider the -15 or -10 variants. The 84-PLCC package requires a socket or careful reflow profiling because of the J-lead thermal mass, and JTAG chain ordering should be planned before PCB layout to avoid contention with other boundary-scan devices. This page synthesizes distributor pricing as of 2026-09-13, pin-compatible MAX 9000 family alternatives from the same 84-PLCC footprint, and practical design notes drawn from the Altera MAX 9000 datasheet family - information not assembled in any single manufacturer document.

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EPM9320LI84-20N - MAX 9000 CPLD, 320 Macrocells, 84-PLCC | Altera
EPM9320LI84-20N

EPM9320LI84-20N - MAX 9000 CPLD, 320 Macrocells, 84-PLCC | Altera

The Altera EPM9320LI84-20N is a high-density, in-system-programmable Complex Programmable Logic Device (CPLD) from the MAX 9000 family, fabricated on a 5.0-V CMOS EEPROM process and housed in an 84-pin Plastic Leaded Chip Carrier (PLCC, J-lead) package. It delivers 320 macrocells, 60 user I/O pins, pin-to-pin propagation delays as fast as 10 ns (speed grade -10 family) with a -20 speed grade variant targeting 20 ns, and internal counter frequencies up to 118 MHz. The MAX 9000 architecture integrates 6,000 to 12,000 usable gates in a third-generation Multiple Array MatriX (MAX) fabric and supports 5.0-V in-system programmability through an IEEE 1149.1 JTAG interface. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL/GAL-like macrocell arrays with a programmable interconnect network. Within the broader programmable logic taxonomy, CPLDs sit between simple SPLDs (PALs, GALs, 22V10) and higher-density FPGAs, offering deterministic timing, instant-on operation from on-chip EEPROM, and high fan-in logic that makes them ideal for glue logic, bus decoding, and state-machine implementation. CPLDs are widely used as companion devices to microcontrollers, ASICs, and FPGAs. Key differentiating specifications include 320 macrocells (the largest density in the MAX 9000 family), 60 bidirectional user I/O pins distributed across multiple I/O banks, 16 ns propagation delay in this speed grade, and a 118 MHz internal counter frequency. The non-volatile EEPROM configuration cell eliminates the need for external boot PROM and supports 100+ in-system reprogramming cycles per the MAX 9000 family specification. The MAX 9000 architecture organizes logic into Logic Array Blocks (LABs) connected by a programmable interconnect, with each macrocell containing a programmable AND/OR array and a configurable flip-flop. The EEPROM-based configuration provides instant-on behavior at power-up, making the EPM9320LI84-20N well-suited to deterministic boot sequencing in systems that cannot tolerate FPGA-style configuration latency. Typical applications include address decoding and bus-interface glue logic in microprocessor systems, peripheral controllers for ISA/PCI bus designs, state-machine and sequencer replacement for discrete 22V10 or TTL logic, JTAG boundary-scan integration on legacy boards, and industrial control systems requiring 5-V tolerant I/O. Designers choose MAX 9000 parts specifically when deterministic 10-20 ns timing and instant-on EEPROM behavior outweigh the higher gate counts of modern FPGAs. When designing with this device, treat the PLCC-84 socket footprint as fixed (J-lead, 1.27 mm pitch, 30.35 x 30.35 mm body) and verify that the surrounding PCB layout preserves signal-integrity margins on the JTAG TCK/TMS/TDO/TDI lines. For new designs, consider the MAX II or MAX V families, which offer similar instant-on behavior with lower static power; for legacy board repair, the EPM9320LI84-20N remains a direct footprint-compatible replacement. This page synthesizes distributor pricing from Octopart and DigiKey, drop-in alternative listings, and practical design notes that are not available on the bare manufacturer datasheet, giving engineers an engineer-focused reference for sourcing and replacement decisions on the MAX 9000 family.

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EPM9320RC208-10 - MAX 9000 CPLD, 320 Macrocells, 208-RQFP | Altera
EPM9320RC208-10

EPM9320RC208-10 - MAX 9000 CPLD, 320 Macrocells, 208-RQFP | Altera

The Altera EPM9320RC208-10 is a member of the MAX 9000 Complex Programmable Logic Device (CPLD) family, providing 6,000 usable gates and 320 macrocells in a 208-pin RQFP package. According to the verified distributor listings, the device operates from a 5 V supply and is offered in the -10 speed grade, which targets pin-to-pin compatible timing across the family. The part is currently listed by multiple distributors as obsolete/legacy stock, reflecting the maturity of the MAX 9000 series in modern designs. A CPLD (Complex Programmable Logic Device) is a non-volatile, flash- or EPROM-based programmable logic device that sits between simple PAL/GAL devices and FPGAs in the programmable logic hierarchy. CPLDs typically provide deterministic pin-to-pin propagation delays, instant-on behavior, and a small number of high-drive I/O banks, which makes them ideal for glue logic, bus decoding, state-machine implementation, and power-sequencing control. The MAX 9000 family from Altera (now Intel Programmable Solutions Group) was one of the higher-density CPLD families of its era, extending the MAX architecture with more macrocells and broader I/O counts. Key features of the EPM9320RC208-10 include the 208-pin RQFP package (commercial 'RC' suffix denotes commercial temperature range), the 5 V VCCIO/VCCINT core supply typical of the MAX 9000 family, and 320 macrocells organized into Logic Array Blocks (LABs). The device supports in-system programmability via the Altera ByteBlaster or BitBlaster JTAG interface and is supported by the legacy MAX+PLUS II and Quartus design toolchains. The -10 speed grade defines the worst-case pin-to-pin tPD, which is documented in the MAX 9000 datasheet family. Typical applications for this part include legacy glue-logic replacement, address decoding for 8/16/32-bit microprocessor buses (Intel 80x86, Motorola 68k, MIPS), 5V system bus arbitration, and pin-compatible upgrades for earlier -15 or -20 speed grades where timing margin allows. The non-volatile architecture means the device retains configuration without external boot memory, simplifying board design and reducing BOM cost in industrial control and telecom infrastructure. When designing with the EPM9320RC208-10, engineers should note that the MAX 9000 family is in NRND/last-time-buy status and new designs should target MAX II, MAX V, or MAX 10 families instead. For legacy board repair, the -15 and -20 speed grade variants are pin-compatible upgrades that simply derate timing.

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EPM9320RC208-15 - MAX 9000 CPLD 320 Macro Cells 15ns | Altera
EPM9320RC208-15

EPM9320RC208-15 - MAX 9000 CPLD 320 Macro Cells 15ns | Altera

The Altera EPM9320RC208-15 is a MAX 9000 family Complex Programmable Logic Device (CPLD) offering 320 macro cells, 6,000 usable gates, and a 15 ns pin-to-pin propagation delay, housed in a 208-pin RQFP (Power QFP) package. It operates from a 5.0 V supply and supports in-system programmability (ISP) through the built-in IEEE Std. 1149.1 JTAG interface. A CPLD (Complex Programmable Logic Device) is a programmable logic IC that combines multiple PAL-like logic blocks with a programmable interconnect matrix on a single die. CPLDs sit between simple PLDs and FPGAs in the programmable logic hierarchy: they offer deterministic, non-volatile timing (EEPROM-based configuration) and instant-on operation, unlike SRAM-based FPGAs that require external configuration memory. The MAX 9000 family is built on Altera's third-generation Multiple Array MatriX (MAX) architecture, which uses EEPROM cells for configuration storage, giving the device non-volatile operation without a configuration PROM. The EPM9320RC208-15 provides 320 macro cells organized into logic array blocks (LABs), with 6,000 usable gates for implementing glue logic, state machines, bus interfaces, and address decoding. Its 15 ns pin-to-pin delay (speed grade -15) supports system clock rates up to approximately 117.6 MHz for the -15 grade, making it suitable for legacy 5 V TTL/CMOS logic consolidation. The 208-pin RQFP package provides up to 160 user I/O pins, enabling wide bus interfacing in a single device. Typical applications include legacy industrial control boards, telecommunications line cards, bus bridging (PCI, VME, ISA), and replacement of discrete 74-series glue logic. Because the device is EEPROM-based, it retains its configuration after power-down and requires no external configuration device, simplifying board design compared to SRAM FPGAs. When designing with the EPM9320RC208-15, note that it is a 5.0 V core device and is not 3.3 V tolerant on all pins without level shifting. The device was declared obsolete by Altera (now Intel) in 2007 per PDN0706, so new designs should consider the MAX II or MAX V families; however, the EPM9320RC208-15 remains in demand for sustaining existing 5 V designs. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet.

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EPM9320RC208-15N - MAX 9000 CPLD 320 Macro Cells | Intel
EPM9320RC208-15N

EPM9320RC208-15N - MAX 9000 CPLD 320 Macro Cells | Intel

The Intel EPM9320RC208-15N is a MAX 9000 family Complex Programmable Logic Device (CPLD) with 6,000 usable gates, 320 macro cells, and a 15 ns pin-to-pin propagation delay, housed in a 208-pin RQFP (PowerQuad Flat Pack) package. It operates from a 5.0 V supply and supports a maximum clock frequency of 117.6 MHz. A CPLD (Complex Programmable Logic Device) is a programmable logic IC that combines the architectural flexibility of a field-programmable gate array with the non-volatile, instant-on behavior of a PAL. CPLDs sit in the programmable logic hierarchy between simple PLDs and FPGAs: CPLD -> programmable logic device -> digital logic IC -> semiconductor. The MAX 9000 family is built on Altera's third-generation Multiple Array MatriX (MAX) architecture, using CMOS EEPROM cells for configuration storage, which means the device retains its logic configuration without an external boot PROM. Key features include 320 macro cells organized into 16 logic array blocks, 484 flip-flops, and 128 configurable I/O lines that support both 3.3 V and 5 V operation. The 15 ns propagation delay and 117.6 MHz maximum clock rate make the device suitable for glue logic, bus interfacing, and state-machine implementations that do not require the density of an FPGA. In-system programmability (ISP) is provided through a built-in IEEE Std. 1149.1 JTAG interface, allowing field reconfiguration without removing the device from the board. The MAX 9000 architecture uses a programmable interconnect array to route signals between logic array blocks, giving deterministic timing that simplifies worst-case delay analysis compared with segmented FPGA routing. The EEPROM configuration is non-volatile, so the device is live within microseconds of power-up, an advantage in systems that cannot tolerate the configuration latency of SRAM-based FPGAs. Typical applications include industrial control backplanes, telecommunications line cards, test-and-measurement instrumentation, and legacy system maintenance where the EPM9320 footprint is already qualified. The 5 V tolerant I/O also allows direct interfacing to older TTL logic without level shifters. When designing with this device, verify that the 208-pin RQFP land pattern matches the 0.5 mm terminal pitch and provide adequate decoupling on each VCC pin. Because the part is a mature MAX 9000 device, designers should confirm lifecycle availability before committing to new production. This page synthesizes distributor pricing, drop-in alternatives, and practical design notes not found in the manufacturer datasheet, giving engineers a single reference for replacement and sourcing decisions.

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EPM9320RC208-20 - 320-Macrocell MAX 9000 CPLD, 20ns | Altera
EPM9320RC208-20

EPM9320RC208-20 - 320-Macrocell MAX 9000 CPLD, 20ns | Altera

The Altera EPM9320RC208-20 is a 320-macrocell, 132-I/O CMOS EEPROM-based Complex Programmable Logic Device (CPLD) from the MAX 9000 family, housed in a 208-pin RQFP (exposed-pad BFQFP) package. Built on Altera's third-generation Multiple Array Matrix (MAX) architecture, it delivers a maximum pin-to-pin propagation delay (tPD) of 20 ns at 5.0 V and integrates approximately 6,000 usable gates with in-system programmability (ISP) via the built-in IEEE Std. 1149.1 JTAG interface. The -20 suffix denotes the 20 ns commercial speed grade. A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL-like macrocell blocks with a programmable interconnect matrix, sitting in the programmable logic hierarchy between simple SPLDs/GALs and higher-density FPGAs. CPLDs are favored for glue-logic, bus-interface, state-machine, and power-on control tasks where deterministic timing, fast input-to-output response, and instant-on (zero-config-time) operation are required. The MAX 9000 family extends this concept to higher densities than earlier MAX 5000/7000 generations while retaining the predictable timing that makes CPLDs the preferred choice for asynchronous logic replacement. Key features of the EPM9320RC208-20 include 320 macrocells organized across 20 logic array blocks (LABs), 132 user I/O pins, 5.0 V in-system programmability through the JTAG-compliant IEEE 1149.1 boundary-scan interface, and a commercial 0 °C to 70 °C operating-temperature range. The exposed-pad RQFP-208 package provides a thermal path for moderate dissipation in surface-mount designs, and the EEPROM process allows unlimited reprogramming cycles without an external configuration memory. The device operates from a single 4.75 V to 5.25 V supply, simplifying integration into legacy 5 V logic systems. Architecturally, the MAX 9000 device combines high-density AND-OR PLA-style logic with fast, deterministic interconnect, giving every macrocell a fixed, predictable delay independent of the design's routing complexity. This contrasts sharply with SRAM-based FPGAs, whose interconnect delays vary with placement. The 132 available I/O pins are 5 V-tolerant within the supply range, supporting TTL and CMOS interfacing without level shifters, and each pin is JTAG-controlled for boundary-scan testability. Typical applications for the EPM9320RC208-20 include 5 V glue-logic consolidation in industrial controllers, address decoding and bus-interface bridging in legacy microprocessor systems, peripheral control logic in telecommunications and networking equipment, and state-machine replacement in instrumentation. Its instant-on non-volatile behavior makes it especially suitable for safety-critical boot logic that must be valid before any host processor runs. When designing with this part, observe the 4.75 V to 5.25 V supply window and keep all inputs within the absolute maximum ratings specified in the datasheet; the exposed thermal pad must be soldered to a sufficient copper area to keep junction temperature within the commercial 0 °C to 70 °C range. Use Altera's MAX+PLUS II or Quartus II legacy support tools to fit designs, and verify JTAG chain order when multiple devices share the same boundary-scan port. This page synthesizes distributor pricing, same-package drop-in alternatives, and practical 5 V glue-logic design notes for the EPM9320RC208-20 - information not consolidated in the Altera datasheet alone.

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EPM9320RC208-20N - MAX 9000 CPLD 320 Macro Cells 5V | Altera
EPM9320RC208-20N

EPM9320RC208-20N - MAX 9000 CPLD 320 Macro Cells 5V | Altera

The Altera EPM9320RC208-20N is a MAX 9000 family Complex Programmable Logic Device (CPLD) offering 6,000 usable gates and 320 macro cells with a 20 ns pin-to-pin propagation delay, housed in a 208-pin RQFP (PowerQuad II) package. It operates from a 5.0 V supply and supports in-system programmability (ISP) through the built-in IEEE Std. 1149.1 JTAG interface. A CPLD (Complex Programmable Logic Device) is a programmable logic IC that combines multiple programmable logic array blocks and a programmable interconnect matrix on a single die, allowing designers to implement custom combinational and sequential logic without fabricating an ASIC. Within the logic IC hierarchy, a CPLD sits between simple PLDs (PAL/GAL) and FPGAs: CPLDs offer deterministic, non-volatile timing with instant-on operation, while FPGAs provide higher logic density at the cost of external configuration memory. The MAX 9000 family is built on Altera's third-generation Multiple Array MatriX (MAX) architecture with EEPROM-based configuration. Key features of the EPM9320RC208-20N include 320 macro cells organized into 20 logic array blocks, 6,000 usable gates, a 20 ns maximum pin-to-pin delay (tPD), and a maximum operating frequency of 100 MHz. The device provides 168 user I/O pins in the 208-pin RQFP package and is configured via EEPROM, so it retains its logic configuration without external boot memory. The 5.0 V core and I/O supply simplifies interfacing to legacy 5 V TTL and CMOS logic. The MAX 9000 architecture uses a programmable interconnect array (PIA) to route signals between logic array blocks, giving predictable, fixed timing independent of routing. Each macro cell contains a flip-flop with programmable clock, clock enable, preset, and clear, plus product-term logic for combinatorial functions. This architecture is well suited to glue logic, bus interfacing, and state-machine implementations where deterministic timing matters more than raw gate count. Typical applications include legacy industrial control boards, ISA/VME bus interface logic, address decoding and chip-select generation, and replacement of discrete 74-series glue logic in long-lifecycle systems. The 5 V operation and 20 ns speed grade make it a natural fit for retrofits of existing 5 V designs. When designing with this device, note that the 20 ns speed grade is the slowest of the EPM9320 family; timing-critical paths should be verified against the tPD and tSU/tCO specifications in the manufacturer datasheet. The RQFP-208 package requires careful thermal and signal-integrity layout for the 168 I/O pins. This page synthesizes distributor availability, drop-in alternatives, and practical design notes not found in the manufacturer datasheet, giving engineers a single reference for second-sourcing this legacy CPLD.

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