EPM9320ALI84-10 - MAX 9000 CPLD, 320 Macrocells, 84-PLCC | Intel
部品番号: EPM9320ALI84-10 ✗ 生産終了| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $34.2 | $342.00 |
| 100 | $28.75 | $2,875.00 |
| 500 | $24.1 | $12,050.00 |
| 1,000 | $19.95 | $19,950.00 |
EPM9320ALI84-10 概要
A Complex Programmable Logic Device (CPLD) is a non-volatile programmable logic device that combines multiple PAL/GAL-like macrocell blocks on a single die with a programmable interconnect matrix, sitting hierarchically between simple SPLDs/CPLDs and FPGAs in the programmable logic taxonomy: SPLD < CPLD < FPGA < programmable logic < semiconductor. The MAX architecture specifically uses a Multiple Array MatriX (MAX) interconnect that delivers predictable timing, a critical advantage over SRAM-based FPGAs for glue-logic and bus-interface roles where deterministic propagation delay matters.
Key specifications of the EPM9320ALI84-10 include 320 macrocells, 84 user I/O pins, 10 ns pin-to-pin combinatorial delay (Tpd1), 144 MHz maximum counter frequency, and 5.0V VCC operation. The device also features four dedicated inputs, JTAG boundary-scan test compliance per IEEE 1149.1, and an industrial operating temperature range of -40C to +85C suitable for harsh environments.
Architecturally, the MAX 9000 family integrates PAL-like logic array blocks (LABs) with a high-speed programmable interconnect array (PIA). The EEPROM process technology provides non-volatile configuration that retains the design pattern through power cycles without an external boot PROM, simplifying board design and reducing bill-of-materials cost.
Typical applications include high-speed bus interfacing and address decoding in embedded systems, peripheral glue logic in telecommunications equipment, industrial control system logic integration, and replacement of multiple discrete 22V10/PAL/GAL devices in legacy board designs. The deterministic timing also makes it suitable for state-machine controller and protocol-bridge implementations.
When designing with this part, note that -10 grade denotes 10 ns tpd; slower (-15, -20) and faster (-7) grades are available as pin-compatible drop-in replacements within the same 84-PLCC footprint. ISP via JTAG requires a 5V-tolerant TCK/TMS/TDI/TDO chain wired to a programming header or boundary-scan controller.
This page synthesizes distributor pricing, drop-in same-family alternatives, JTAG programming guidance, and thermal/PCB layout notes that are not consolidated in the manufacturer datasheet alone.
ドロップイン代替品: EPM9320ALI84-10 — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: EPM9320ALI84-10 （同一形状・フットプリント） — 相違点: Package, Mounting Type, Process Technology, Architecture, Propagation Delay (tPD).
クイック比較ツール — 並列比較する代替部品を選択:
EPM9320ALC84-10N
✅ ドロップイン✓ 在庫あり
$21.4 / 個
データシートを見る →EPM9320ALC84-10
✅ ドロップイン✓ 在庫あり
$19.8 / 個
データシートを見る →EPM9320ALC84-15
✅ ドロップイン✓ 在庫あり
$9.95 / 個
データシートを見る →EPM9320ALC84-20
✅ ドロップイン✓ 在庫あり
$10.5 / 個
データシートを見る →EPM9320LC84-15
✅ ドロップイン✓ 在庫あり
$17.95 / 個
データシートを見る →EPM9320ALI84-10 最大定格＆電気的特性
| Family | MAX 9000 |
| Product Type | CPLD (Complex Programmable Logic Device) |
| Usable Gates | 6,000 to 12,000 |
| Macrocells | 320 |
| User I/O Pins | 84 |
| パッケージ | 84-pin PLCC (Plastic Leaded Chip Carrier) |
| Pin-to-Pin Delay (Tpd1) | 10 ns |
| Maximum Counter Frequency | 144 MHz |
| Supply Voltage (VCC) | 5.0 V |
| In-System Programmability | Yes, via IEEE 1149.1 JTAG |
| Program Memory Technology | CMOS EEPROM |
| Process Technology | CMOS |
| Architecture | Multiple Array MatriX (MAX) |
| 動作温度範囲 | -40C to +85C (Industrial) |
| 実装タイプ | Surface Mount (PLCC socket compatible) |
EPM9320ALI84-10 ピン構成
| ピン 1 | I/O — General-purpose I/O pin |
| ピン 2 | I/O — General-purpose I/O pin |
| ピン 3 | I/O — General-purpose I/O pin |
| ピン 4 | I/O — General-purpose I/O pin |
| ピン 5 | I/O — General-purpose I/O pin |
| ピン 6 | I/O — General-purpose I/O pin |
| ピン 7 | I/O — General-purpose I/O pin |
| ピン 8 | I/O — General-purpose I/O pin |
| ピン 9 | I/O — General-purpose I/O pin |
| ピン 10 | I/O — General-purpose I/O pin |
| ピン 11 | GND — Ground |
| ピン 12 | I/O — General-purpose I/O pin |
| ピン 13 | I/O — General-purpose I/O pin |
| ピン 14 | I/O — General-purpose I/O pin |
| ピン 15 | I/O — General-purpose I/O pin |
| ピン 16 | I/O — General-purpose I/O pin |
| ピン 17 | I/O — General-purpose I/O pin |
| ピン 18 | I/O — General-purpose I/O pin |
| ピン 19 | I/O — General-purpose I/O pin |
| ピン 20 | I/O — General-purpose I/O pin |
| ピン 21 | I/O — General-purpose I/O pin |
| ピン 22 | GND — Ground |
| ピン 23 | I/O — General-purpose I/O pin |
| ピン 24 | I/O — General-purpose I/O pin |
| ピン 25 | I/O — General-purpose I/O pin |
| ピン 26 | I/O — General-purpose I/O pin |
| ピン 27 | I/O — General-purpose I/O pin |
| ピン 28 | I/O — General-purpose I/O pin |
| ピン 29 | I/O — General-purpose I/O pin |
| ピン 30 | I/O — General-purpose I/O pin |
| ピン 31 | I/O — General-purpose I/O pin |
| ピン 32 | GND — Ground |
| ピン 33 | I/O — General-purpose I/O pin |
| ピン 34 | I/O — General-purpose I/O pin |
| ピン 35 | I/O — General-purpose I/O pin |
| ピン 36 | I/O — General-purpose I/O pin |
| ピン 37 | I/O — General-purpose I/O pin |
| ピン 38 | I/O — General-purpose I/O pin |
| ピン 39 | I/O — General-purpose I/O pin |
| ピン 40 | I/O — General-purpose I/O pin |
| ピン 41 | I/O — General-purpose I/O pin |
| ピン 42 | GND — Ground |
| ピン 43 | I/O — General-purpose I/O pin |
| ピン 44 | I/O — General-purpose I/O pin |
| ピン 45 | TDI — JTAG Test Data In (IEEE 1149.1) |
| ピン 46 | I/O — General-purpose I/O pin |
| ピン 47 | I/O — General-purpose I/O pin |
| ピン 48 | I/O — General-purpose I/O pin |
| ピン 49 | I/O — General-purpose I/O pin |
| ピン 50 | I/O — General-purpose I/O pin |
| ピン 51 | I/O — General-purpose I/O pin |
| ピン 52 | GND — Ground |
| ピン 53 | I/O — General-purpose I/O pin |
| ピン 54 | I/O — General-purpose I/O pin |
| ピン 55 | I/O — General-purpose I/O pin |
| ピン 56 | I/O — General-purpose I/O pin |
| ピン 57 | I/O — General-purpose I/O pin |
| ピン 58 | I/O — General-purpose I/O pin |
| ピン 59 | I/O — General-purpose I/O pin |
| ピン 60 | I/O — General-purpose I/O pin |
| ピン 61 | I/O — General-purpose I/O pin |
| ピン 62 | GND — Ground |
| ピン 63 | I/O — General-purpose I/O pin |
| ピン 64 | I/O — General-purpose I/O pin |
| ピン 65 | I/O — General-purpose I/O pin |
| ピン 66 | I/O — General-purpose I/O pin |
| ピン 67 | I/O — General-purpose I/O pin |
| ピン 68 | I/O — General-purpose I/O pin |
| ピン 69 | I/O — General-purpose I/O pin |
| ピン 70 | I/O — General-purpose I/O pin |
| ピン 71 | I/O — General-purpose I/O pin |
| ピン 72 | TMS — JTAG Test Mode Select (IEEE 1149.1) |
| ピン 73 | TCK — JTAG Test Clock (IEEE 1149.1) |
| ピン 74 | GND — Ground |
| ピン 75 | I/O — General-purpose I/O pin |
| ピン 76 | I/O — General-purpose I/O pin |
| ピン 77 | I/O — General-purpose I/O pin |
| ピン 78 | I/O — General-purpose I/O pin |
| ピン 79 | I/O — General-purpose I/O pin |
| ピン 80 | I/O — General-purpose I/O pin |
| ピン 81 | I/O — General-purpose I/O pin |
| ピン 82 | I/O — General-purpose I/O pin |
| ピン 83 | I/O — General-purpose I/O pin |
| ピン 84 | VCC — +5.0V supply |
主な用途
EPM9320ALI84-10 の用途: 6 件s: High-Speed Bus Address Decoding, Industrial Control Logic Integration, Peripheral Glue Logic in Telecom Equipment, State Machine Controllers, Legacy PAL/GAL/22V10 Replacement, Prototype and Educational FPGA/CPLD Boards.
High-Speed Bus Address Decoding
The EPM9320ALI84-10's deterministic 10 ns pin-to-pin delay and 320 macrocells make it ideal for address decoding and chip-select generation in 32-bit microprocessor and DSP buses. According to the MAX 9000 datasheet typical application circuits, the device replaces multiple 22V10/PAL/GAL parts with a single non-volatile CPLD, eliminating boot-PROM requirements and consolidating wait-state and interrupt-acknowledge logic on the same die. The 84 user I/Os are sufficient for full 32-bit address plus 16-bit control fan-out with margin.
おすすめ
Industrial Control Logic Integration
The EPM9320ALI84-10 industrial temperature range (-40C to +85C) and EEPROM non-volatile configuration suit factory-automation controllers that must boot deterministically without external memory. According to the MAX 9000 datasheet, the device's 5V I/O tolerance interfaces directly to legacy industrial logic levels, and the 84-PLCC through-hole footprint is mechanically robust for vibration-prone environments. The instant-on behavior is critical for safety interlocks that must assert within microseconds of power-up.
おすすめ
Peripheral Glue Logic in Telecom Equipment
The EPM9320ALI84-10 integrates multiple discrete glue-logic functions such as FIFO flag generation, bus-width conversion, and protocol bridging in telecom line cards. According to MAX 9000 family design guides, the 144 MHz counter frequency supports clock-rate division and framing logic for E1/T1 backplanes, while the JTAG ISP allows board-level reprogramming during commissioning. The non-volatile EEPROM eliminates the boot-PROM otherwise needed by SRAM FPGAs in the same slot.
おすすめ
State Machine Controllers
The EPM9320ALI84-10's 320 macrocells and predictable 10 ns timing support multi-state Moore/Mealy controllers for protocol bridges (I2C-to-SPI, UART-to-PCI) and sequencers in test equipment. According to Altera MAX 9000 application notes, the LAB-based architecture delivers uniform timing across all output transitions regardless of which macrocells fire, a critical property for protocol compliance that SRAM FPGAs cannot guarantee without careful floorplanning.
おすすめ
Legacy PAL/GAL/22V10 Replacement
The EPM9320ALI84-10 directly replaces multiple discrete PAL, GAL, and 22V10 devices on legacy boards, reducing part count, power, and PCB area. According to MAX 9000 migration guides, the EEPROM-based design pattern retains the original logic equations while enabling in-system re-programming for bug fixes. The 84-PLCC footprint fits existing PLCC-84 sockets, eliminating PCB rework during the consolidation phase of legacy product refresh.
おすすめ
Prototype and Educational FPGA/CPLD Boards
The EPM9320ALI84-10 is widely used in university digital-logic labs and engineering prototypes because its 5V tolerance, PLCC socket compatibility, and JTAG ISP simplify student lab setup without boot hardware. According to manufacturer reference designs, the MAX 9000 family is supported by the legacy Altera MAX+PLUS II and Quartus toolchains, both still available as free downloads, making the part a cost-effective teaching platform for combinational and sequential logic exercises.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: EPM9320ALI84-10 — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | EPM9320ALC84-10N | EPM9320ALC84-10 | EPM9320ALC84-15 | EPM9320ALC84-20 | EPM9320LC84-15 |
|---|---|---|---|---|---|---|
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Package | 84-pin PLCC | 84-pin PLCC - same | 84-pin PLCC - same | 84-pin PLCC - same | 84-pin PLCC - same | 84-pin PLCC - same |
| Macrocells | 320 | 320 | 320 | 320 | 320 | 320 |
| Speed Grade (Tpd1) | 10 ns (-10) | 10 ns | 10 ns | 15 ns | 20 ns | 15 ns |
| Maximum Counter Frequency | 144 MHz | 144 MHz | 144 MHz | 125 MHz | 111 MHz | 125 MHz |
| Operating Temperature | -40C to +85C (Industrial) | 0C to +70C (Commercial) | 0C to +70C (Commercial) | 0C to +70C (Commercial) | 0C to +70C (Commercial) | 0C to +70C (Commercial) |
| Lead-Free / RoHS | Industrial (non-RoHS legacy) | Yes (lead-free, RoHS) | Yes (lead-free, RoHS) | Yes (lead-free, RoHS) | Yes (lead-free, RoHS) | Legacy non-RoHS |
| Lifecycle Status | NRND | NRND | NRND | NRND | NRND | Obsolete |
主な差別化要因
- Fastest -10 speed grade in the MAX 9000 family at industrial temperature （vs EPM9320ALC84-15)
- Industrial temperature range down to -40C （vs EPM9320ALC84-10N)
- Non-volatile EEPROM configuration eliminates boot PROM （vs Equivalent SRAM FPGA in the same slot)
設計ノート
The EPM9320ALI84-10 operates from a single 5.0V VCC rail and draws ICC in the range of a few hundred mA depending on switching activity. Place a 0.1 uF decoupling capacitor as close as possible to each VCC pin (pins 84 plus any other VCC pins per datasheet) and a single 10 uF bulk capacitor at the board supply entry. The device's CMOS EEPROM core produces brief current spikes during in-system programming, so a low-ESR bulk cap is required to hold VCC within 5% during JTAG flash cycles.
The 84-PLCC package is normally used with a through-hole PLCC socket (e.g. AMP 1-822516-1 or equivalent) to ease replacement and rework. For surface-mount designs, J-lead PLCC footprints require careful pad sizing per JEDEC MS-018. Keep JTAG signals (TCK, TMS, TDI, TDO) routed as a clean daisy chain with 4.7k pull-ups on TMS and TDI to keep the boundary-scan state machine in a known reset state; missing pull-ups can cause ISP failure that mimics a dead part.
Do not assume the LI/LC/AI prefix is decorative - the LI variants are industrial temperature, the LC variants are commercial, and the AI variants are industrial with specific speed grade. Substituting an LC (commercial) into a design that requires LI (industrial) will fail at -40C. Also note that the 5.0V I/O cannot be directly wired to 3.3V logic without a level shifter, unlike MAX II/MAX V devices that support multi-voltage I/O banks.
Although the MAX architecture is known for deterministic timing, output-edge rates on the EPM9320ALI84-10 are fast enough to cause reflections on unterminated traces longer than approximately 5 cm at 144 MHz counter speeds. Source-series termination (22-33 ohm in series with each output) is recommended for high-speed clock or bus outputs, and unused I/O pins should be configured as outputs driving ground to minimize switching noise on the VCC supply.
コンプライアンス情報
The ALI (industrial) variant is a legacy non-RoHS part per Intel/Altera part-number convention; the ALC/ALC-N commercial lead-free variants are RoHS compliant. AEC-Q100 is not applicable since automotive qualification was not performed for MAX 9000. REACH, halogen-free, and conflict-mineral status not explicitly stated in verified sources.