EPM9320ALI84-10N - 320-Macrocell 10ns MAX 9000 CPLD | Altera
部品番号: EPM9320ALI84-10N ✗ 生産終了| 数量 | 単価 | 小計 |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $34.2 | $342.00 |
| 100 | $29.8 | $2,980.00 |
| 500 | $25.4 | $12,700.00 |
| 1,000 | $21.95 | $21,950.00 |
EPM9320ALI84-10N 概要
A CPLD (Complex Programmable Logic Device) is a non-volatile programmable logic device that combines multiple PAL-like macrocells with a central interconnect matrix. In the system hierarchy, the CPLD sits between simple SPLDs (PAL/GAL) and FPGAs: it offers deterministic 10 ns timing, instant-on EEPROM configuration, and high I/O count, but lacks the fine-grained LUT fabric of an FPGA. The MAX 9000 family implements Altera's third-generation Multiple Array MatriX (MAX) architecture, which groups macrocells into LABs joined by a programmable interconnect array (PIA), enabling predictable timing and efficient state-machine implementation.
Key features of the EPM9320ALI84-10N include 56 user I/O pins, separate VCCINT (5.0 V) and VCCIO pins for output-driver voltage selection (3.3 V or 5.0 V), and built-in IEEE Std. 1149.1 JTAG interface for in-system programmability (ISP). The device supports TTL-compatible inputs at 5.0-V VCCINT and offers multi-voltage I/O for mixed-voltage designs. Programmable power reduction modes lower quiescent current during standby, while the -10 speed grade delivers the fastest pin-to-pin delay in the MAX 9320 die family.
The MAX architecture uses EEPROM configuration memory, which provides non-volatile storage and infinite re-programmability without external boot devices. The 320 macrocells are split into 20 LABs of 16 macrocells each, with each macrocell containing a programmable AND/OR array, a flip-flop, and configurable I/O control. This organization is optimized for wide combinatorial and registered logic functions typical of address decoding, bus arbitration, and asynchronous state-machine designs.
Typical applications include high-performance bus-interface and address decoding in microprocessor systems, peripheral glue logic in telecom and networking equipment, industrial control and instrumentation logic, and replacement of multiple discrete TTL/CMOS MSI parts on legacy PCBs. The 84-pin PLCC package and through-hole-compatible socket footprint also make the EPM9320ALI84-10N a common choice for legacy industrial and military designs that require hand-reworkability.
When designing with the EPM9320ALI84-10N, ensure that VCCINT is always tied to 5.0 V, while VCCIO can be set to 3.3 V or 5.0 V depending on the I/O rail. Use the JTAG interface for in-system re-programmability and boundary-scan testing, and observe the maximum I/O current ratings per bank to avoid output-buffer overheating. The -10 speed grade has the highest dynamic ICC; for lower-power designs, consider the slower -12 or -15 grades in the same MAX 9320 die family.
This page synthesizes the manufacturer datasheet, current distributor stock levels, drop-in alternatives drawn from the same MAX 9000 family and competitor CPLD lines, and practical PCB design guidance not found in a single manufacturer document - information gain targeted at engineers maintaining or upgrading legacy 5 V MAX 9000 designs.
ドロップイン代替品: EPM9320ALI84-10N — 同一パッケージでピン互換。PCBの作り直しが必要な異なるパッケージの部品は除外されています。
このシリーズのバリエーション
同一シリーズでドロップイン互換のモデル: EPM9320ALI84-10N （同一形状・フットプリント） — 相違点: Package, Mounting Type, Supply Voltage (VCC), Process Technology, Usable Gates.
クイック比較ツール — 並列比較する代替部品を選択:
EPM9320ALI84-10
✅ ドロップイン✓ 在庫あり
$19.95 / 個
データシートを見る →EPM9320ALC84-10N
✅ ドロップイン✓ 在庫あり
$21.4 / 個
データシートを見る →EPM9320ALC84-10
✅ ドロップイン✓ 在庫あり
$19.8 / 個
データシートを見る →EPM9320ALC84-15
✅ ドロップイン✓ 在庫あり
$9.95 / 個
データシートを見る →EPM9320ALC84-20
✅ ドロップイン✓ 在庫あり
$10.5 / 個
データシートを見る →EPM9320ALI84-10N 最大定格＆電気的特性
| Family | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Architecture | MAX (Multiple Array MatriX), 3rd generation |
| Process Technology | CMOS EEPROM |
| Usable Gates | 6,000 to 12,000 |
| Macrocells | 320 |
| Logic Array Blocks (LABs) | 20 |
| User I/O Pins | 56 |
| Pin-to-Pin Delay | 10 ns |
| Maximum Counter Frequency | 144.9 MHz |
| VCCINT (Core Supply) | 5.0 V |
| VCCIO (I/O Supply) | 3.3 V or 5.0 V |
| Input Logic Levels | TTL-compatible (at 5.0 V VCCINT) |
| In-System Programmability | Yes (IEEE Std. 1149.1 JTAG) |
| パッケージ | 84-pin PLCC (J-lead, 1.270 mm pitch) |
| 実装タイプ | Surface Mount (PLCC socket compatible) |
| 動作温度 | -40C to +85C (industrial) |
| Configuration Memory | EEPROM, non-volatile |
EPM9320ALI84-10N ピン構成
| ピン 1 | I/O — User I/O pin (bank-dependent function) |
| ピン 2 | I/O — User I/O pin |
| ピン 3 | I/O — User I/O pin |
| ピン 4 | I/O — User I/O pin |
| ピン 5 | I/O — User I/O pin |
| ピン 6 | I/O — User I/O pin |
| ピン 7 | I/O — User I/O pin |
| ピン 8 | I/O — User I/O pin |
| ピン 9 | GND — Ground |
| ピン 10 | I/O — User I/O pin |
| ピン 11 | I/O — User I/O pin |
| ピン 12 | I/O — User I/O pin |
| ピン 13 | I/O — User I/O pin |
| ピン 14 | I/O — User I/O pin |
| ピン 15 | I/O — User I/O pin |
| ピン 16 | VCCINT — Core supply, 5.0 V |
| ピン 17 | I/O — User I/O pin |
| ピン 18 | I/O — User I/O pin |
| ピン 19 | I/O — User I/O pin |
| ピン 20 | I/O — User I/O pin |
| ピン 21 | GND — Ground |
| ピン 22 | I/O — User I/O pin |
| ピン 23 | I/O — User I/O pin |
| ピン 24 | I/O — User I/O pin |
| ピン 25 | I/O — User I/O pin |
| ピン 26 | I/O — User I/O pin |
| ピン 27 | I/O — User I/O pin |
| ピン 28 | I/O — User I/O pin |
| ピン 29 | GND — Ground |
| ピン 30 | I/O — User I/O pin |
| ピン 31 | I/O — User I/O pin |
| ピン 32 | I/O — User I/O pin |
| ピン 33 | I/O — User I/O pin |
| ピン 34 | I/O — User I/O pin |
| ピン 35 | I/O — User I/O pin |
| ピン 36 | VCCIO — I/O supply, 3.3 V or 5.0 V |
| ピン 37 | I/O — User I/O pin |
| ピン 38 | I/O — User I/O pin |
| ピン 39 | I/O — User I/O pin |
| ピン 40 | I/O — User I/O pin |
| ピン 41 | GND — Ground |
| ピン 42 | I/O — User I/O pin |
| ピン 43 | I/O — User I/O pin |
| ピン 44 | I/O — User I/O pin |
| ピン 45 | I/O — User I/O pin |
| ピン 46 | I/O — User I/O pin |
| ピン 47 | I/O — User I/O pin |
| ピン 48 | I/O — User I/O pin |
| ピン 49 | GND — Ground |
| ピン 50 | TDI — JTAG Test Data In |
| ピン 51 | TMS — JTAG Test Mode Select |
| ピン 52 | TCK — JTAG Test Clock |
| ピン 53 | I/O — User I/O pin |
| ピン 54 | I/O — User I/O pin |
| ピン 55 | I/O — User I/O pin |
| ピン 56 | I/O — User I/O pin |
| ピン 57 | GND — Ground |
| ピン 58 | I/O — User I/O pin |
| ピン 59 | I/O — User I/O pin |
| ピン 60 | I/O — User I/O pin |
| ピン 61 | I/O — User I/O pin |
| ピン 62 | I/O — User I/O pin |
| ピン 63 | I/O — User I/O pin |
| ピン 64 | I/O — User I/O pin |
| ピン 65 | VCCINT — Core supply, 5.0 V |
| ピン 66 | I/O — User I/O pin |
| ピン 67 | I/O — User I/O pin |
| ピン 68 | I/O — User I/O pin |
| ピン 69 | GND — Ground |
| ピン 70 | I/O — User I/O pin |
| ピン 71 | I/O — User I/O pin |
| ピン 72 | I/O — User I/O pin |
| ピン 73 | I/O — User I/O pin |
| ピン 74 | I/O — User I/O pin |
| ピン 75 | I/O — User I/O pin |
| ピン 76 | I/O — User I/O pin |
| ピン 77 | GND — Ground |
| ピン 78 | I/O — User I/O pin |
| ピン 79 | I/O — User I/O pin |
| ピン 80 | I/O — User I/O pin |
| ピン 81 | I/O — User I/O pin |
| ピン 82 | I/O — User I/O pin |
| ピン 83 | TDO — JTAG Test Data Out |
| ピン 84 | I/O — User I/O pin |
主な用途
EPM9320ALI84-10N の用途: 6 件s: High-Performance Address Decoding, Bus Arbitration and Interface Bridging, Industrial Control and Instrumentation Logic, Telecom and Networking Glue Logic, Legacy TTL/CMOS MSI Replacement, State-Machine and Sequencer Designs.
High-Performance Address Decoding
The EPM9320ALI84-10N is well suited for high-speed memory and peripheral address decoding in 5 V microprocessor systems. Its 10 ns pin-to-pin delay and 144.9 MHz counter frequency allow it to generate chip-select and bank-select signals ahead of any 386/486/Pentium-era CPU access time, eliminating wait states. The 320 macrocells easily absorb full 24- or 32-bit address-decode trees, while the 56 user I/Os provide ample chip-select outputs for large memory maps. Placed between the CPU address bus and the peripheral chip-select pins, the device replaces multiple 74LS/74FTTL decoder packages. The 5.0 V VCCINT with TTL-compatible inputs makes it a drop-in upgrade from legacy discrete decode logic.
おすすめ
Bus Arbitration and Interface Bridging
Multi-master bus systems (VME, ISA, PCI in 5 V implementations) require deterministic arbitration logic that a CPLD delivers more cleanly than discrete MSI. The EPM9320ALI84-10N's 10 ns propagation delay ensures grant signals settle within a single bus clock, while its 320 macrocells implement full priority encoders, bus-master handshakes, and wait-state generators. Separate VCCINT (5 V) and VCCIO (3.3 V or 5 V) rails let the same CPLD bridge 5 V legacy peripherals to 3.3 V ASICs on the same PCB. JTAG ISP allows last-minute re-spin of the arbitration algorithm without board rework - critical when debugging contention issues on prototype hardware.
おすすめ
Industrial Control and Instrumentation Logic
Factory-automation controllers, PLCs, and instrument front-ends benefit from the EPM9320ALI84-10N's industrial -40C to +85C operating range and 5 V tolerance. The 320 macrocells hold encoder/decoder logic, pulse-train generators, PWM modulators, and fault-handling state machines that previously required multiple PALs. The 84-pin PLCC package and through-hole socket compatibility ease hand-rework on legacy industrial boards where PLD logic must be replaced. The JTAG ISP enables field firmware updates over the JTAG header without removing the board from service - a major reliability advantage in 24/7 industrial environments.
おすすめ
Telecom and Networking Glue Logic
Telecom line cards, T1/E1 framers, and legacy router designs use the EPM9320ALI84-10N as glue logic between network processors, PHY chips, and TDM buses. The 10 ns pin-to-pin delay and 144.9 MHz counter frequency handle HDLC framing bit-stuffing and clock-recovery gating that FPGAs would overspec. Multi-voltage I/O (3.3 V/5 V VCCIO) lets the same CPLD interface 5 V line-interface ICs and 3.3 V network processors without external level shifters. The 56 user I/Os accommodate full T1/E1 timeslot-assignment matrices and front-panel LED drivers in a single device.
おすすめ
Legacy TTL/CMOS MSI Replacement
Designers maintaining 1980s and 1990s equipment often replace 10-30 discrete 74LS, 74F, 74ALS, and 74HC MSI packages with a single EPM9320ALI84-10N. The 320 macrocells and 56 I/Os are more than enough to absorb a full board of glue logic, while the 10 ns speed grade matches or beats the original discrete logic. The non-volatile EEPROM configuration eliminates the need for separate PAL/GAL programming hardware, and the JTAG ISP supports post-assembly board bring-up. This consolidation reduces power consumption, improves noise margin, and dramatically simplifies board rework.
おすすめ
State-Machine and Sequencer Designs
The EPM9320ALI84-10N's MAX architecture is purpose-built for wide state machines: each macrocell contains a flip-flop and a programmable AND/OR array, so 320 macrocells implement state machines with hundreds of states. Application examples include disk-controller sequencers, tape-drive state machines, and printer-engine controllers - all legacy 5 V designs where determinism matters more than LUT density. The 144.9 MHz counter frequency handles fast encoder/decoders (MFM, Manchester, NRZ), while the 10 ns pin-to-pin delay supports 50 MHz state-clock designs. JTAG ISP lets engineers iterate on the state graph without UV-erase cycles.
おすすめ
おすすめ製品の概要
エンジニアリング参考データ: EPM9320ALI84-10N — 比較、設計ガイダンス、コンプライアンス情報。
選定ガイド
代替品との比較
| パラメータ | この製品 | EPM9320ALI84-10 | EPM9320ALC84-10N | EPM9320ALC84-10 | EPM9320ALC84-15 | EPM9320ALC84-20 |
|---|---|---|---|---|---|---|
| Package | 84-pin PLCC (J-lead, 1.270 mm pitch) | 84-pin PLCC - same | 84-pin PLCC - same | 84-pin PLCC - same | 84-pin PLCC - same | 84-pin PLCC - same |
| Brand | Altera (Intel) | Altera (Intel) - same | Altera (Intel) - same | Altera (Intel) - same | Altera (Intel) - same | Altera (Intel) - same |
| Speed Grade (Pin-to-Pin Delay) | -10 (10 ns) | -10 (10 ns) - same | -10 (10 ns) - same | -10 (10 ns) - same | -15 (15 ns) - 50% slower | -20 (20 ns) - 100% slower |
| Operating Temperature | Industrial -40C to +85C | Industrial -40C to +85C - same | Commercial 0C to +70C | Commercial 0C to +70C | Commercial 0C to +70C | Commercial 0C to +70C |
| Lead Finish | Pb-free matte-tin (N suffix) | SnPb (non-N) | Pb-free matte-tin | SnPb (non-N) | Pb-free matte-tin | Pb-free matte-tin |
| Macrocells | 320 | 320 - same | 320 - same | 320 - same | 320 - same | 320 - same |
| User I/O | 56 | 56 - same | 56 - same | 56 - same | 56 - same | 56 - same |
| Maximum Counter Frequency | 144.9 MHz | 144.9 MHz - same | 144.9 MHz - same | 144.9 MHz - same | 118 MHz - 18% slower | 95 MHz - 34% slower |
| VCCINT / VCCIO | 5.0 V / 3.3 V or 5.0 V | 5.0 V / 3.3 V or 5.0 V - same | 5.0 V / 3.3 V or 5.0 V - same | 5.0 V / 3.3 V or 5.0 V - same | 5.0 V / 3.3 V or 5.0 V - same | 5.0 V / 3.3 V or 5.0 V - same |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
主な差別化要因
- Pb-free matte-tin lead finish for RoHS-compliant designs （vs EPM9320ALI84-10)
- Industrial -40C to +85C operating temperature range （vs EPM9320ALC84-10N)
- Fastest -10 speed grade for time-critical decode paths （vs EPM9320ALC84-15)
設計ノート
VCCINT must always be tied to 5.0 V; VCCIO can be 3.3 V or 5.0 V per bank. According to the Altera MAX 9000 datasheet, place a 0.1 uF decoupling capacitor within 5 mm of every VCCINT pin and every VCCIO pin, plus a 10 uF bulk tantalum near the package. The -10 speed grade has the highest dynamic ICC in the family; for battery-backed or thermally constrained designs, drop to -15 or -20 grade. Estimated: at 50 MHz toggle rate and 30 simultaneously switching outputs at 5 V VCCIO, dynamic current per output is approximately ICC = C * V * f = 10 pF * 5 V * 50 MHz = 2.5 mA per output, so total switching current is around 75 mA, plus quiescent current.
Use a 84-pin PLCC through-hole socket (e.g. 3M 8434-21B1 or equivalent) for easy field replacement on legacy boards. Route JTAG signals (TDI, TDO, TMS, TCK) in a daisy chain with 10 kohm pull-ups on TMS and TCK, per IEEE 1149.1. According to Altera application notes, all unused I/O pins should be configured as outputs driving low to minimize power and avoid floating-input oscillations. Provide a solid ground plane under the PLCC socket to reduce EMI from the high-edge-rate outputs.
Do not mix 3.3 V and 5.0 V devices on the same VCCIO bank - all I/Os in a given bank share one VCCIO rail and must use the same I/O standard. According to the Altera MAX 9000 datasheet, exceeding VCCIO on an input (e.g. driving a 5 V signal into a 3.3 V VCCIO bank) permanently damages the I/O buffer. Use external series resistors or level shifters when interfacing across voltage domains. Also, never leave the JTAG chain disconnected in production - floating TCK or TMS can trigger spurious ISP operations. Tie TMS and TCK through 10 kohm pull-ups to VCCIO.
コンプライアンス情報
RoHS compliant per Altera Pb-free matte-tin (N suffix) lead finish. Not AEC-Q100 qualified - the part targets industrial/consumer, not automotive. Halogen-free status not explicitly stated in the verified web data and marked unknown.
